AQA 7517 · Paper 2 · 4.7.1

Von Neumann vs
Harvard Architecture

Computer architecture · Memory models · Bus types · Section 4.7

WHAT YOU'LL LEARN

Von Neumann model · Stored program concept · Harvard architecture · Von Neumann bottleneck

AQA SPEC LINK

4.7.1 — Von Neumann and Harvard architecture

Von Neumann Architecture

The Von Neumann Model

Proposed by John von Neumann (1945). The key innovation: stored program concept — programs stored in the same memory as data, and can be modified by the computer itself.

CPU, single shared memory (for both instructions and data), single bus connecting them

Instructions and data share the same address space and the same bus

Still the basis of most modern general-purpose computers (PCs, laptops, servers)

Stored Program Concept

Why "Stored Program" Matters

Before von Neumann: computers were hard-wired for specific tasks — changing the program meant rewiring the machine

Stored program: program instructions held in RAM along with data — can be loaded, changed, and reused

Makes general-purpose computing possible — one machine can run any program

Instructions are data — can be copied, modified, passed as parameters (enables compilers, OS, virtual machines)

Von Neumann Bottleneck

The Von Neumann Bottleneck

Since instructions AND data share the same bus, only one can be fetched at a time. As CPUs get faster, they spend more time waiting for memory — the bus becomes a bottleneck.

CPU speed doubles every ~18 months (Moore's Law); memory bandwidth improves much slower

Partial solutions: cache memory, pipelining, wider data buses, burst transfers

Harvard architecture addresses this more directly

Harvard Architecture

Separate memory and buses for instructions and data

Can fetch instruction AND read/write data simultaneously — no bottleneck

Instruction memory is often read-only (ROM in microcontrollers) — more secure

Used in: microcontrollers (PIC, Arduino), DSPs (digital signal processors), ARM processors (using separate L1 caches)

More complex and expensive — separate memory units and buses needed

Comparison

Von Neumann vs Harvard

Feature	Von Neumann	Harvard
Memory	Shared (instructions + data)	Separate memories
Buses	Single shared bus	Separate buses
Throughput	Bottleneck exists	Higher throughput
Used in	PCs, laptops, servers	Microcontrollers, DSPs

Modern CPUs

Modified Harvard in Modern CPUs

Most modern CPUs use a modified Harvard architecture — separate L1 instruction and data caches, but a unified L2/L3 cache and main memory. Best of both worlds.

Separate L1 I-cache and D-cache → Harvard benefit (fetch simultaneously)

Shared L2/L3 and RAM → Von Neumann flexibility (load any data)

Used in: Intel Core, AMD Ryzen, Apple Silicon, ARM Cortex

The Bus

System Bus Components

ADDRESS BUS (unidirectional)

CPU sends memory address it wants to read/write. Width determines addressable memory (32-bit = 4 GB, 64-bit = 16 EB)

DATA BUS (bidirectional)

Carries the actual data between CPU and memory. Width (8/16/32/64-bit) determines throughput per cycle

CONTROL BUS (bidirectional)

Carries signals: read/write, clock, reset, interrupt, bus request/grant

AQA Exam Style

Practice Question

AQA 7517 — Paper 2 Style

(a) Describe the stored program concept. [2]
(b) Explain what is meant by the 'Von Neumann bottleneck' and how it arises. [3]
(c) Give TWO differences between Von Neumann and Harvard architectures. [2]
(d) State ONE reason why Harvard architecture is used in microcontrollers rather than von Neumann. [1]

[8 marks]

2 marks

(a) Programs (instructions) are stored in memory alongside data [1]; instructions can be fetched, modified, and executed by the computer without hardware changes [1]

3 marks

(b) In Von Neumann, instructions and data share the same bus [1]. The CPU can only transfer data or fetch instructions, not both simultaneously [1]. As CPUs became faster than memory, the bus became the limiting factor [1]

2 marks

(c) Any 2: Harvard has separate memory vs shared / Harvard has separate buses / Harvard can fetch instruction and data simultaneously / Harvard instruction memory often read-only

1 mark

(d) Higher throughput (can fetch instruction and data simultaneously) / simpler, more predictable timing for real-time control applications

Summary

Key Points to Remember

Von Neumann — stored program concept; single shared memory and bus; bottleneck problem

Harvard — separate memory/buses for instructions and data; no bottleneck; used in microcontrollers

Modern CPUs — modified Harvard (separate L1 caches) + Von Neumann (shared L2/L3 and RAM)

System buses — Address bus (where), Data bus (what), Control bus (how)

Address bus width = 32-bit → 4 GB addressable memory; 64-bit → essentially unlimited

🎉 Lesson complete — move to the quiz!