AQA 7517 · Paper 2 · 4.7.2

FDE Cycle &
Registers

Fetch-Decode-Execute · PC · MAR · MDR · CIR · ACC

WHAT YOU'LL LEARN

Fetch-Decode-Execute cycle · All 5 key registers · Interrupts · CPU components

AQA SPEC LINK

4.7.2 — The processor: FDE cycle, registers, and how they are used

The Registers

Key CPU Registers

PC

Program Counter — holds address of next instruction to fetch

MAR

Memory Address Register — address being read from/written to

MDR

Memory Data Register — data read from or to be written to memory

CIR

Current Instruction Register — holds instruction being decoded/executed

ACC

Accumulator — stores results of ALU operations (add, AND, etc.)

Fetch Stage

The Fetch Stage

1. PC → MAR (copy address from PC to MAR)

2. Memory[MAR] → MDR (read instruction from memory into MDR)

3. MDR → CIR (copy instruction to Current Instruction Register)

4. PC ← PC + 1 (increment PC to point to next instruction)

Decode & Execute

Decode & Execute Stages

DECODE

Control Unit splits CIR into opcode (what to do) and operand (what to do it to). Determines which circuit to activate.

EXECUTE

Appropriate action performed:
• Arithmetic/logic → ALU processes using ACC
• Memory read → MAR gets operand, MDR gets data → ACC
• Memory write → data from ACC → MAR address
• Branch → PC ← operand address (if condition met)

CPU Components

CPU Internal Components

Control Unit (CU) — orchestrates FDE cycle; sends control signals to all components

ALU (Arithmetic Logic Unit) — performs arithmetic (+, −, ×, ÷) and logic (AND, OR, NOT, XOR, compare)

Registers — ultra-fast on-chip storage (PC, MAR, MDR, CIR, ACC, general-purpose registers)

Clock — generates pulses that synchronise all CPU operations; speed measured in Hz (GHz)

Cache — fast memory on/near CPU to buffer frequently used data/instructions from RAM

Interrupts

Interrupts & Interrupt Handling

An interrupt is a signal to the CPU requesting immediate attention. At the end of each FDE cycle, CPU checks for interrupts.

If interrupt: CPU saves current state (context) to stack

PC ← address of Interrupt Service Routine (ISR)

ISR executes (handles the interrupt source)

Context restored from stack; original program resumes

FDE Worked Example

Tracing Through FDE

      PC=100, instruction at 100: ADD 200

      FETCH: MAR←100, MDR←ADD 200, CIR←ADD 200, PC←101

      DECODE: opcode=ADD, operand=200

      EXECUTE: MAR←200, MDR←[200], ACC←ACC+MDR

After execute, PC=101 so next cycle fetches instruction at address 101 automatically.

Register Summary

Which Register Does What

Register	Full Name	Purpose
PC	Program Counter	Address of next instruction
MAR	Memory Address Register	Address to read from / write to
MDR	Memory Data Register	Data read/written from/to memory
CIR	Current Instruction Register	Instruction being decoded/executed
ACC	Accumulator	ALU result store

AQA Exam Style

Practice Question

AQA 7517 — Paper 2 Style

(a) State the purpose of the Program Counter (PC) and describe what happens to it during the fetch stage. [2]
(b) Describe the role of the Memory Address Register (MAR) during the fetch stage. [2]
(c) An interrupt occurs. Describe the steps taken by the CPU to handle it. [4]

[8 marks]

2 marks

(a) PC holds the address of the next instruction to be fetched [1]. During fetch: the address in PC is copied to MAR; PC is then incremented by 1 to point to the next instruction [1]

2 marks

(b) MAR receives the address from PC [1] and sends it to memory via the address bus so the correct instruction can be read [1]

4 marks

(c) At end of FDE cycle, interrupt is detected [1]. CPU saves current state (context) — contents of registers including PC — to stack [1]. PC is loaded with address of the Interrupt Service Routine (ISR) [1]. ISR executes; on completion, context is restored from stack and original program continues [1]

Summary

Key Points to Remember

Fetch — PC→MAR, memory→MDR, MDR→CIR, PC+1

Decode — CU splits CIR into opcode + operand

Execute — ALU operates on ACC; memory reads/writes via MAR/MDR; branches update PC

Registers — PC (next address), MAR (address), MDR (data), CIR (instruction), ACC (result)

Interrupt: save context → ISR runs → restore context → resume

🎉 Lesson complete — move to the quiz!