AQA 7517 · Paper 2 · 4.7.3

CPU Performance:
Clock, Cores, Cache
& Pipelining

What makes a CPU faster · Section 4.7

WHAT YOU'LL LEARN

Clock speed · Multi-core · Cache levels · Pipelining concept · Performance trade-offs

AQA SPEC LINK

4.7.3 — Factors affecting CPU performance

Clock Speed

The clock generates regular pulses that synchronise CPU operations. Clock speed = number of FDE cycles per second. Measured in Hz (modern CPUs: 3–5 GHz).

3.5 GHz = 3,500,000,000 cycles per second

Faster clock → more instructions per second → faster performance

Limitation: faster clock = more heat; requires better cooling; thermal throttling may reduce speed

Overclocking: running CPU beyond rated speed — risky (heat, instability)

Multiple Cores

Multi-Core Processors

A core is a complete CPU unit. Modern processors contain multiple cores (2, 4, 8, 16+), each capable of independently executing instructions.

8-core CPU can run 8 threads simultaneously (true parallelism)

Software must be written to use multiple cores — poorly parallelised code won't benefit

More cores better for: video editing, 3D rendering, servers, scientific computing

Single-threaded tasks (many games) benefit more from higher clock speed on one core

Cache Memory

Cache Memory Levels

L1 Cache (~32–128 KB, ~1ns)

Fastest, smallest, closest to core. Split into instruction and data cache (modified Harvard). One per core.

L2 Cache (~256 KB – 1 MB, ~5ns)

Larger and slower than L1. Usually one per core. Bridges L1 and L3.

L3 Cache (~4–64 MB, ~15ns)

Shared across all cores. Much larger but slower. Reduces trips to RAM (60–100ns).

Cache Hits & Misses

Cache Hit Rate

Cache hit — data found in cache; fast access (L1 ~1 ns)

Cache miss — data not in cache; must go to next level (L2 → L3 → RAM); much slower

Modern CPUs achieve ~95% L1 hit rates for well-structured code

Locality of reference — programs tend to reuse the same data/code recently accessed (temporal locality) or nearby data (spatial locality)

Larger cache = more data fits = higher hit rate = faster overall performance

Pipelining

Pipelining overlaps the FDE stages of consecutive instructions, like an assembly line. While one instruction executes, the next is being decoded, and the one after is being fetched.

Without pipeline (serial):

F1

D1

E1

F2

D2

E2

With pipeline (concurrent):

F1

D1
F2

E1
D2
F3

E2
D3

E3

Throughput ≈ 1 instruction per clock cycle (vs. 3 cycles without pipeline)

Pipeline Hazards

Data Hazard

Next instruction needs result of previous instruction that hasn't completed yet. Solution: stall pipeline (insert "nop"), or data forwarding.

Control Hazard (Branch)

Conditional branch — CPU doesn't know which instruction comes next until branch is evaluated. Solution: branch prediction.

Branch Prediction

CPU guesses branch outcome and speculatively executes. If wrong: pipeline flushed, performance penalty.

Performance Summary

Factors Affecting Performance

Factor	How it helps	Limitation
Clock speed ↑	More cycles/sec	Heat generation
More cores	True parallelism	Software must parallelise
Larger cache	Fewer RAM accesses	Cost, physical size
Pipelining	~1 instruction/cycle	Branch hazards

AQA Exam Style

Practice Question

AQA 7517 — Paper 2 Style

(a) State TWO ways that increasing the number of CPU cores can improve performance. [2]
(b) Explain how pipelining improves CPU throughput. [3]
(c) Explain why cache memory improves CPU performance. Include reference to cache hit and miss in your answer. [3]
(d) Give ONE disadvantage of increasing clock speed. [1]

[9 marks]

2 marks

(a) Multiple threads can execute simultaneously / parallel tasks run faster / OS can assign different tasks to different cores

3 marks

(b) Pipelining allows multiple FDE stages to overlap [1]; while one instruction is executing, the next is decoded, and the one after is fetched [1]; throughput approaches one instruction per clock cycle rather than one per three cycles [1]

3 marks

(c) Cache is much faster than RAM [1]. A cache hit means data is available in nanoseconds rather than tens of nanoseconds from RAM [1]. Cache misses require slow RAM access, so higher hit rates mean fewer RAM accesses and faster overall execution [1]

1 mark

(d) Increased heat production / requires more cooling / risk of thermal throttling or hardware damage

Summary

Key Points to Remember

Clock speed — faster = more FDE cycles/second; limited by heat

Cores — multiple cores = true parallelism; software must be written for it

Cache — L1 (fastest, ~32KB), L2, L3 (slowest, ~32MB); hit rate critical to performance

Pipelining — overlaps F, D, E stages; throughput ≈ 1 instruction/cycle; hazards require mitigation

Real-world CPUs combine all four techniques simultaneously

🎉 Lesson complete — move to the quiz!