CAIE 9618 · Paper 1 · Topic 1.3.1

CPU Architecture

ALU · Control Unit · Registers · System Buses · Performance Factors

CSZone Cambridge International AS & A Level Computer Science 9618

The Von Neumann Architecture

Stored Program Concept

The Von Neumann architecture is the model used by most modern computers. Both program instructions and data are stored in the same memory (RAM) and fetched by the CPU for execution.

KEY UNITS

• ALU — Arithmetic and Logic Unit
• CU — Control Unit
• Registers — fast on-chip storage
• Memory (RAM/cache)
• System buses (data, address, control)

STORED PROGRAM CONCEPT

Instructions stored in memory as binary. CPU fetches, decodes, and executes them sequentially. Program can be changed by loading different instructions into memory — no rewiring needed.

CPU Components: ALU & CU

The Processing Core

ALU — ARITHMETIC & LOGIC UNIT

Performs all arithmetic operations (+, -, ×, ÷) and logical operations (AND, OR, NOT, XOR, shifts). All calculations pass through the ALU. Results stored in the Accumulator (ACC).

CU — CONTROL UNIT

Directs operations of the CPU. Sends control signals to fetch instructions from memory, decode them, and coordinate the ALU and registers. Does not itself process data.

CPU Registers

Fast On-Chip Storage

CORE REGISTERS — MUST KNOW ALL 6

PC Program Counter — holds address of NEXT instruction to be fetched

MAR Memory Address Register — holds address of memory location being accessed

MDR Memory Data Register — holds data being read from or written to memory

CIR Current Instruction Register — holds the instruction currently being decoded/executed

ACC Accumulator — holds result of ALU operations

SR Status Register — holds flag bits (zero, negative, overflow, carry)

System Buses

Communication Pathways

DATA BUS

Carries actual data between CPU, memory, and I/O devices. Bidirectional (data flows both ways). Width (bits) determines how much data transferred per cycle — wider = faster.

ADDRESS BUS

Carries memory addresses from CPU to memory. Unidirectional (CPU → memory only). Width determines maximum addressable memory: 32-bit = 2³² = 4 GB addresses.

CONTROL BUS

Carries control signals (read/write, clock, interrupt, reset). Bidirectional. Coordinates activities across all components.

CPU Performance Factors

What Makes a CPU Faster?

Clock Speed (GHz) — number of clock cycles per second. Higher = more instructions per second. Heat and power consumption increase with clock speed.

Number of Cores — each core can execute instructions independently. Allows true parallel processing. More cores ≠ always faster (depends on software parallelism).

Cache Size — fast SRAM on the CPU chip. Larger cache = more frequently needed data kept close to CPU = fewer slow RAM accesses.

Word Length — number of bits CPU processes in one operation. 64-bit CPU processes more data per cycle than 32-bit.

Bus Width — wider data bus transfers more data per cycle; wider address bus allows more addressable memory.

Exam Practice

Cambridge-style questions

Question 1

State the purpose of each of the following registers: PC, MAR, MDR, CIR.

4 marks

1 mark

PC (Program Counter): holds the memory address of the next instruction to be fetched

1 mark

MAR (Memory Address Register): holds the address of the memory location currently being accessed (read or written)

1 mark

MDR (Memory Data Register): holds data that has been read from memory, or data waiting to be written to memory

1 mark

CIR (Current Instruction Register): holds the instruction that is currently being decoded and executed

Exam Practice

Question 2

Explain the difference between the data bus and the address bus. Include bus direction in your answer.

4 marks

1 mark

Data bus carries actual data/instructions between CPU, memory, and I/O devices

1 mark

Data bus is bidirectional — data flows in both directions (read and write)

1 mark

Address bus carries memory addresses — specifying where data is to be read from or written to

1 mark

Address bus is unidirectional — addresses only sent from CPU to memory, never in reverse

Common Mistakes

Don't lose easy marks

1

Saying the PC holds the current instruction — the PC holds the address of the next instruction to be fetched. The CIR holds the current instruction being executed. This mix-up is very common.

2

Saying the address bus is bidirectional — the address bus is unidirectional (CPU → memory only). Only the data bus and control bus are bidirectional.

3

Confusing more cores = always faster — multiple cores only improve performance if the software is written to use parallel processing. A single-threaded program will not benefit from extra cores.

Topic Summary — 1.3.1

What You Need to Know

CPU COMPONENTS

ALU: arithmetic + logic operations
CU: directs CPU operations, control signals
Registers: ultra-fast on-chip storage
Cache: fast SRAM between CPU and RAM

REGISTERS

PC → address of NEXT instruction
MAR → address being accessed
MDR → data read/write buffer
CIR → current instruction
ACC → ALU result · SR → flags

SYSTEM BUSES

Data bus: carries data, bidirectional
Address bus: carries addresses, unidirectional
Control bus: signals, bidirectional
Wider buses = faster data transfer

PERFORMANCE FACTORS

Clock speed (GHz) · Number of cores
Cache size · Word length
Bus width (data + address)

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Next Video

1.3.2

The FDE Cycle

Fetch · Decode · Execute — Register by Register

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