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CAIE 9618 · Paper 1 · Topic 1.3.2

The Fetch-Decode-
Execute Cycle

Register-level detail · Interrupts · Pipelining

CSZone Cambridge International AS & A Level Computer Science 9618
FETCH Stage

Retrieving the Instruction from Memory

1
Contents of PC copied to MAR via address bus → MAR now holds address of next instruction
2
PC incremented by 1 → ready to point to the instruction after the one being fetched
3
Instruction at address in MAR is read from memory → placed on data bus → stored in MDR
4
Contents of MDR copied to CIR → CIR now holds the instruction to be decoded
DECODE Stage

Interpreting the Instruction

The Control Unit decodes the instruction held in the CIR. It splits the instruction into its opcode (operation to perform) and operand (data or address to use).
OPCODE
The operation part — tells the CPU what to do (e.g. ADD, LOAD, STORE, JUMP). The CU uses this to generate the correct control signals.
OPERAND
The data part — a memory address, register reference, or immediate value that the operation acts on. May be a direct or indirect address.
EXECUTE Stage

Carrying Out the Instruction

The CU issues control signals to the appropriate component. The type of execution depends on the opcode:
ALU
Arithmetic/logic: CU sends operand to ALU. ALU performs operation. Result stored in ACC. Status flags updated in SR.
LOAD
Address placed in MAR. Data fetched from memory → MDR → ACC.
STORE
Address to MAR. Contents of ACC → MDR → written to memory at that address.
JUMP
Operand (target address) loaded into PC directly — overwriting incremented value. Next fetch uses new address.
Interrupts

Handling Urgent Events

An interrupt is a signal to the CPU that an event requires immediate attention (e.g. I/O complete, hardware error, timer expired). The CPU checks for interrupts at the end of each FDE cycle.
1
Interrupt signal received — CPU checks Interrupt Service Register (ISR)
2
If interrupt has higher priority than current task, CPU saves current state (PC, registers) to stack
3
PC loaded with address of Interrupt Service Routine (ISR)
4
ISR executes; on completion, saved state is restored from stack and program resumes from where it was interrupted
Exam Practice

Cambridge-style questions

Question 1
Describe the steps of the FETCH stage of the FDE cycle, naming all registers involved.
4 marks
1 mark
Contents of PC copied to MAR (via address bus) — MAR now holds the address of the next instruction
1 mark
PC is incremented by 1 — ready to point to the following instruction
1 mark
Instruction at address in MAR is fetched from memory and placed in MDR (via data bus)
1 mark
Contents of MDR copied to CIR — CIR now holds the instruction ready for decoding
Common Mistakes

Don't lose easy marks

1
Saying the PC increments before being copied to MAR — the PC is copied to MAR first, then incremented. If it incremented first, the CPU would fetch the wrong (next-next) instruction.
2
Saying the CIR holds the address of the instruction — the CIR holds the actual instruction (opcode + operand). The MAR holds addresses. Don't confuse these two registers.
3
For a JUMP instruction, saying the PC is incremented as normal — in a jump, the PC is overwritten with the target address in the operand. There is no increment for a jump.
Topic Summary — 1.3.2

The FDE Cycle at a Glance

FETCH
1. PC → MAR (address bus)
2. PC incremented
3. Memory[MAR] → MDR (data bus)
4. MDR → CIR
DECODE
CU decodes CIR
Splits into opcode (what) + operand (data/address)
CU generates control signals
EXECUTE
ALU ops: result → ACC, flags → SR
LOAD: memory → MDR → ACC
STORE: ACC → MDR → memory
JUMP: operand address → PC
INTERRUPTS
Checked after each FDE cycle
State saved to stack
PC → ISR address
ISR runs, state restored on return
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1.3.3
Assembly Language
Mnemonics · Operands · Instruction Set · Modes
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