CAIE 9618 · Paper 1 · Topic 1.5.5

RISC vs CISC

Instruction Sets · Pipelining · Architecture Trade-offs · Modern Context

CSZone Cambridge International AS & A Level Computer Science 9618

CISC — Complex Instruction Set Computer

Many, Powerful Instructions

CISC processors have a large set of complex instructions, each capable of performing multi-step operations (e.g. one instruction to multiply two values and store the result to memory). Examples: x86 (Intel, AMD).

ADVANTAGES

Complex tasks done in fewer instructions. Easier to write assembly code (programmer does less). Compiler has powerful instructions to choose from. Less program memory needed.

DISADVANTAGES

Complex instructions take variable number of clock cycles. Harder to pipeline efficiently. Large instruction decode unit. More complex chip design — higher cost and power use.

RISC — Reduced Instruction Set Computer

Few, Simple Instructions

RISC processors have a small set of simple instructions that each execute in exactly one clock cycle. Relies on the compiler to combine these simple instructions to perform complex tasks. Examples: ARM (most mobile devices).

ADVANTAGES

Each instruction takes exactly 1 clock cycle → ideal for pipelining. Simpler hardware design → cheaper, lower power. Better performance per watt — ideal for mobile/embedded.

DISADVANTAGES

Requires more instructions to complete complex tasks. More program code = more memory used. Greater demand on compiler to optimise instruction sequences.

Pipelining

Overlapping FDE Cycle Stages

Pipelining allows the CPU to start fetching the next instruction while the current one is being decoded or executed — overlapping stages of the FDE cycle to increase throughput. RISC is ideal for pipelining because all instructions take 1 cycle.

WITHOUT PIPELINING (sequential):  Inst 1: F-D-E  →  Inst 2: F-D-E  →  Inst 3: F-D-E
WITH PIPELINING (overlapped):
Clock:  1   2   3   4   5   6   7
Inst1:  F  D  E
Inst2:     F  D  E
Inst3:        F  D  E

RISC vs CISC Comparison

Side-by-Side

Feature	RISC	CISC
Instruction count	Small (few hundred)	Large (hundreds to thousands)
Instruction complexity	Simple	Complex, multi-step
Clock cycles per instruction	1 (fixed)	Variable (1 to many)
Pipelining	Excellent	Harder (variable cycles)
Registers	Many	Fewer
Code size	Larger (more instructions)	Smaller (fewer instructions)
Power consumption	Lower	Higher
Examples	ARM, RISC-V, MIPS	x86 (Intel Core, AMD Ryzen)
Main use	Mobile, embedded, tablets	Desktop, laptop, server

Exam Practice

Cambridge-style questions

Question 1

Explain why RISC processors are better suited to pipelining than CISC processors.

4 marks

1 mark

RISC instructions each take a fixed, single clock cycle to execute

1 mark

This uniformity allows the pipeline stages (fetch, decode, execute) to be cleanly overlapped — each stage is ready for the next instruction at precisely the right time

1 mark

CISC instructions take a variable number of clock cycles — this causes pipeline stalls as later stages must wait for slower instructions to complete

1 mark

RISC's simpler decode stage means less hardware is needed for decoding, leaving more transistors available for pipeline stages and registers

Common Mistakes

Don't lose easy marks

1

Saying RISC is always faster than CISC — RISC CPUs often run at similar or slower clock speeds, but are more efficient per watt. Modern x86 CISC CPUs (Intel/AMD) are extremely fast. It's not a simple speed comparison — it's about design philosophy.

2

Saying CISC has fewer registers — it's the opposite: RISC processors typically have many more general-purpose registers than CISC, because RISC relies on registers rather than complex memory-addressing instructions.

3

Saying pipelining means two instructions run at once — pipelining overlaps different stages of multiple instructions simultaneously. At any given moment, one instruction is being fetched, another decoded, another executed — they are in different stages, not the same.

Topic Summary — 1.5.5

What You Need to Know

CISC

Many complex instructions
Variable clock cycles per instruction
Hard to pipeline · Fewer registers
Examples: x86 (Intel/AMD) · Desktop/Server

RISC

Few simple instructions · 1 cycle each
Excellent pipelining · Many registers
Lower power, smaller chip
Examples: ARM · Mobile/Embedded/Tablets

PIPELINING

Overlap FDE cycle stages across instructions
Fetch inst 2 while decoding inst 1
RISC ideal: all instructions = 1 cycle
CISC: variable cycles cause pipeline stalls

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