CAIE 9618 · Paper 3 · Topic 3.3.1

Processors

RISC vs CISC · Pipelining · Parallel Processing · Multi-Core · GPU · Harvard Architecture

CSZone Cambridge International AS & A Level Computer Science 9618

RISC vs CISC

Reduced vs Complex Instruction Sets

Feature	RISC	CISC
Instruction set	Small — few simple instructions	Large — many complex instructions
Instruction size	Fixed length (e.g. 32-bit)	Variable length
Clock cycles per instruction	1 (mostly)	1 to many
Registers	Many general-purpose registers	Fewer registers
Memory access	LOAD/STORE only — no mem-to-mem ops	Many instructions access memory directly
Pipelining	Easy — uniform instruction length	Harder — variable instruction length
Compiler complexity	More complex — compiler must combine	Simpler — one instruction does more
Power consumption	Lower — fewer transistors	Higher
Examples	ARM (phones, tablets, Apple Silicon)	Intel x86, AMD (PCs, laptops)

Pipelining

Overlapping Instruction Stages

Pipelining overlaps the FDI (Fetch-Decode-Execute) stages of multiple instructions simultaneously — like an assembly line. Without pipelining, each instruction must complete all stages before the next begins.

4-stage pipeline (Fetch · Decode · Execute · Write-back):

Cycle	1	2	3	4	5	6	7
I1	F	D	E	W
I2		F	D	E	W
I3			F	D	E	W

Pipeline hazards: A branch instruction can invalidate instructions already in the pipeline (pipeline flush needed). Data hazards occur when an instruction needs the result of an instruction still in the pipeline.

Parallel Processing & Multi-Core

Multiple Instructions at the Same Time

MULTI-CORE PROCESSOR

Multiple CPU cores on a single chip

Each core independently fetches, decodes, executes instructions

Cores share cache (L2/L3) and main memory

OS schedules threads across cores

Benefits: better multitasking, faster parallel programs

GPU — GRAPHICS PROCESSING UNIT

Thousands of small, simple cores — massively parallel

Each core handles simple float operations (pixel shading)

SIMD — Single Instruction Multiple Data: same operation on thousands of data items simultaneously

Used for: graphics rendering, AI training, crypto mining, scientific simulation

HARVARD ARCHITECTURE

Separate instruction memory and data memory buses — allows simultaneous fetch of instruction and data. Used in DSPs and microcontrollers. Von Neumann uses shared bus (slower, simpler).

Exam Practice

Cambridge-style questions

Question 1

Describe two features of RISC processors that make them more suitable than CISC processors for use in mobile phones. [4]

1+1

RISC processors use a smaller instruction set with fixed-length instructions, which means fewer transistors are needed — this results in lower power consumption, extending battery life in mobile phones.

1+1

RISC processors are easier to pipeline because all instructions are the same length and execute in one clock cycle — this gives higher throughput per clock cycle without requiring a higher frequency (which would increase heat and power use in a mobile device).

Common Mistakes

Don't lose easy marks

1

Saying "RISC is always faster than CISC" — not true. CISC can do more per instruction, while RISC does more instructions per second. Modern CPUs blur the line — x86 (CISC) processors internally translate CISC to RISC-like micro-ops. The mark scheme wants specific feature comparisons, not general "RISC is better" claims.

2

Confusing pipelining with parallel processing — pipelining overlaps stages of sequential instructions (one instruction at a time in each stage). Parallel processing runs completely independent instruction streams simultaneously (multi-core / multi-processor). They are different techniques.

3

Describing GPU as "a better CPU" — a GPU has thousands of simple, limited-purpose cores optimised for parallel float operations. A CPU has fewer but much more powerful, general-purpose cores better at sequential processing. Neither is universally better — they serve different tasks.

Topic Summary — 3.3.1

What You Need to Know

RISC

Small fixed instruction set · 1 cycle/instruction · many registers · LOAD/STORE only · easy to pipeline · low power · ARM (phones)

CISC

Large varied instruction set · multi-cycle instructions · memory-direct operations · harder to pipeline · Intel x86 (PCs)

PIPELINING

Overlaps F/D/E stages of successive instructions. Pipeline hazards: branch flush, data hazard. Easier with RISC (fixed instruction length).

PARALLEL

Multi-core: multiple CPUs on chip. GPU: thousands of small SIMD cores for parallel float operations. Harvard: separate instruction/data buses.

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3.3.2

Virtual Machines

Hypervisors · Types 1 & 2 · Benefits · JVM

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