Describe the roles of the ALU, Control Unit, and key registers (PC, MAR, MDR, CIR, ACC, status register)
Explain the purpose of general purpose registers and why they improve performance
Describe the stored program concept (Von Neumann) and the Von Neumann bottleneck
Distinguish between Von Neumann and Harvard architecture
CPU Components
ALU and Control Unit
Arithmetic Logic Unit (ALU)
Performs arithmetic (add, subtract, multiply, divide), logical (AND, OR, NOT, XOR), and shift operations on binary data.
Control Unit (CU)
Fetches and decodes instructions. Sends control signals to coordinate all CPU operations. Does not perform calculations.
Together, the CU and ALU form the processor core. The CU manages the flow; the ALU does the work.
Registers
Special Purpose Registers
PC — Program Counter: address of the next instruction to fetch; increments during fetch
MAR — Memory Address Register: address being accessed; connected to address bus
MDR — Memory Data Register: data being read/written; connected to data bus
CIR — Current Instruction Register: holds instruction being decoded by the CU
ACC — Accumulator: stores result of most recent ALU operation
Status Register: individual flag bits from the last operation (carry, zero, negative, overflow)
Registers
Status Register Flags
The status register contains individual flag bits set by the outcome of the last arithmetic or logical operation. Conditional branch instructions read these flags to control program flow.
Carry (C) — a carry was produced out of the MSB
Zero (Z) — result is zero (used for equality tests)
Negative (N) — result is negative (MSB = 1)
Overflow (V) — signed result too large for register
Example: after CMP R0, R1 — if Z flag is set, R0 = R1. A BEQ branch then jumps.
Registers
General Purpose Registers
Multiple GPRs (e.g. R0–R15 in ARM) store operands and intermediate results inside the CPU, drastically reducing slow accesses to main memory.
Performance Benefit
Register access: <1 clock cycle. Main memory access: 100–200+ cycles. GPRs eliminate many memory round-trips.
Contrast: Single Accumulator
Older designs used one ACC. Each intermediate result had to be stored to/loaded from memory — much slower.
Architecture
Von Neumann & Harvard
Stored Program Concept (Von Neumann): both program instructions and data are stored together in main memory (RAM) in binary. Programs can be loaded and changed without altering hardware.
Von Neumann Bottleneck: instructions and data share the same memory bus. The CPU cannot simultaneously fetch an instruction and access data — throughput is limited.
Harvard Architecture: separate memories and buses for instructions and data. Avoids the bottleneck; used in embedded systems, DSPs, and microcontrollers.
Bus System
The Three Buses
Address bus — carries memory addresses from CPU to memory. Unidirectional. Width determines max addressable memory: 2n locations for n-bit bus.
Data bus — carries data/instructions between CPU and memory. Bidirectional. Width determines bits transferred per clock cycle (e.g. 64-bit bus transfers 8 bytes at once).
Control bus — carries control signals (read, write, clock, interrupt). Bidirectional. Coordinates all operations between CPU and peripherals.
Wider buses → more data per cycle → higher throughput — key factor in CPU performance.
Exam Practice
OCR H446 Style · 4 marks
Explain the difference between the MAR and the MDR. State which bus each is connected to and describe how they work together during a memory read operation.
[4 marks]
1
MAR (Memory Address Register) holds the memory address of the location being accessed.
1
MAR is connected to the address bus (unidirectional, CPU → memory).
1
MDR (Memory Data Register) holds the data read from or written to that address.
1
During a read: address from MAR placed on address bus → memory retrieves data → data placed on data bus → copied into MDR.
Exam Practice
OCR H446 Style · 3 marks
Explain what is meant by the Von Neumann bottleneck and state one way it can be reduced.
[3 marks]
1
Instructions and data share the same memory bus in Von Neumann architecture.
1
The CPU cannot fetch an instruction and access data simultaneously, limiting throughput / creating a performance bottleneck.
1
Can be reduced by: using cache memory to reduce bus traffic / using Harvard architecture with separate buses / using wider data bus to transfer more per cycle.
Common Mistakes
Don’t Lose Marks
!
Saying the CU performs calculations — it does NOT. Only the ALU performs arithmetic and logical operations; the CU sends control signals.
!
Confusing MAR and MDR: MAR holds the memory address (connected to address bus); MDR holds the data (connected to data bus).
!
Saying the address bus is bidirectional — it is unidirectional, carrying addresses from CPU to memory only.