Explain the role of cache in reducing CPU wait time
Bus System
The Address Bus
Address bus: carries memory addresses from the CPU to memory (and I/O). It is unidirectional — CPU to memory only.
Bus width determines addressable memory: an n-bit address bus can address 2n memory locations. A 32-bit bus = 4 GB max; 64-bit bus = 16 EB max.
Increasing bus width extends the maximum addressable memory space without requiring hardware changes to individual memory cells.
Bus System
The Data and Control Buses
Data Bus
Bidirectional — carries data/instructions between CPU, memory and I/O. Width (e.g. 64-bit) determines how many bits are transferred per clock cycle. Wider = more data per transfer.
Control Bus
Bidirectional — carries control signals: memory read/write, clock signals, bus request/grant, interrupt signals. Coordinates all components on the system bus.
All three buses together form the system bus. Wider buses improve throughput but increase cost and complexity.
Memory
Primary Memory: RAM and ROM
RAM (Random Access Memory)
Volatile — loses data when power removed. Stores current programs and data. DRAM: capacitors, needs refreshing, used for main memory. SRAM: flip-flops, faster, used for cache.
ROM (Read-Only Memory)
Non-volatile — retains data when power removed. Stores firmware/BIOS. Cannot be written during normal operation. Examples: PROM, EPROM, EEPROM.
ROM contains the bootloader: the first program executed when a computer powers on, which initialises hardware and loads the OS from secondary storage into RAM.
Cache
Cache Memory
Cache is small, fast SRAM on or near the CPU. It stores copies of frequently-accessed data/instructions to reduce access to slower main memory (RAM). Exploits temporal locality (recently used) and spatial locality (nearby data).
L1 Cache
Fastest, smallest (4–64 KB). On-chip, per core. ~1 cycle access.
L2 Cache
Larger (256 KB–4 MB). On-chip or near-chip. ~5–10 cycle access.
L3 Cache
Largest (8–64 MB). Shared across cores. ~30–60 cycle access.
Cache
Cache Hit, Miss and Replacement
Cache hit: requested data found in cache. CPU retrieves it directly without accessing RAM — fast.
Cache miss: requested data not in cache. CPU fetches from RAM and copies to cache — slower, but future accesses are faster.
Replacement policy: when cache is full, old data must be evicted. Common policies: LRU (Least Recently Used), LFU (Least Frequently Used).
Hit rate: proportion of accesses satisfied by cache. Higher hit rate = better performance. Increasing cache size generally improves hit rate but at higher cost.
Exam Practice
OCR H446 Style · 4 marks
A computer has a 32-bit address bus and a 64-bit data bus. Explain what these widths mean for (a) the maximum amount of addressable memory, and (b) the amount of data transferred per clock cycle.
[4 marks]
1
32-bit address bus can address 232 = 4,294,967,296 memory locations.
1
If each location stores 1 byte, maximum addressable RAM = 4 GB.
1
A 64-bit data bus transfers 64 bits (8 bytes) of data per clock cycle.
1
A wider data bus increases throughput — more data moved per cycle without increasing clock speed.
Common Mistakes
Don’t Lose Marks
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Saying the address bus is bidirectional — it is unidirectional. Only the data bus and control bus are bidirectional.
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Confusing bus width with clock speed. Wider bus = more data per transfer. Faster clock = more transfers per second. Both affect performance but differently.
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Saying cache replaces RAM — it does not. Cache stores copies of RAM data temporarily. RAM is still the primary memory; cache just reduces average access time.