The Fetch-Execute Cycle | OCR H446

Learning Objectives

By the end of this topic you will be able to:

Describe in detail each step of the Fetch, Decode and Execute stages

State which registers are involved at each stage

Explain how interrupts integrate into the FDE cycle

Trace register values through the FDE cycle for a given instruction

Fetch Stage

Step 1 — Fetch

PC → MAR: contents of the Program Counter (address of next instruction) copied to the Memory Address Register.

Memory → MDR: address bus carries address from MAR to memory. Data at that address is placed on the data bus and loaded into the MDR.

MDR → CIR: the fetched instruction is copied from the MDR to the Current Instruction Register.

PC increments: the Program Counter is incremented by the size of one instruction to point to the next instruction.

Decode & Execute

Steps 2 & 3 — Decode and Execute

Decode

The Control Unit decodes the instruction held in the CIR. It separates the opcode (operation to perform) from the operand (data or address). It generates control signals to direct the appropriate components.

Execute

The decoded instruction is carried out: the ALU performs arithmetic/logic, data is read from or written to memory/registers, or a branch address is loaded into the PC. Result may be stored in ACC or a GPR.

After execute, the CPU checks for interrupts before beginning the next fetch cycle.

Interrupts

Interrupts in the FDE Cycle

An interrupt is a signal sent to the CPU to pause the current task and deal with a higher-priority event. The CPU checks for interrupts at the end of each execute stage.

If an interrupt is flagged: current register values are saved to the stack (context saved).

The PC is loaded with the address of the Interrupt Service Routine (ISR).

The ISR executes. When complete, saved context is restored from the stack and the original program resumes.

Interrupt types: hardware (keyboard, mouse), software (program exception), timer (OS scheduler). Higher priority interrupts can interrupt ISRs (vectored interrupts).

Registers

Register Involvement Summary

Fetch

PC → MAR → (address bus) → Memory → (data bus) → MDR → CIR. PC increments.

Decode

CIR decoded by CU. Opcode identifies operation; operand identifies data/address.

Execute

ALU uses operands from registers. Result stored in ACC or GPR. Branch: PC updated. Memory access: MAR/MDR used.

Interrupt check

Status register checked. If interrupt pending: context saved to stack, PC ← ISR address.

Exam Practice

OCR H446 Style · 5 marks

Describe the steps that occur during the fetch stage of the Fetch-Decode-Execute cycle, including the registers used and the buses involved at each step.

[5 marks]

Contents of the PC (address of next instruction) are copied to the MAR.

The address in the MAR is placed on the address bus and sent to memory.

The instruction at that address is placed on the data bus and loaded into the MDR.

The instruction is copied from the MDR to the CIR.

The PC is incremented to point to the next instruction (ready for next fetch).

Common Mistakes

Don’t Lose Marks

Saying the PC increments during decode or execute — the PC increments during the fetch stage, after the instruction address is copied to the MAR.

Forgetting to mention both the address bus and data bus during the fetch stage. The address bus carries the MAR value; the data bus returns the instruction to the MDR.

Saying interrupts are checked continuously — they are checked at the end of each execute stage, not during fetch or decode.

The Fetch-ExecuteCycle