OCR H446 · Component 1 · 1.1.1

CPU Performance Factors
and Pipelining

OCR A Level Computer Science · cszone.co.uk

H446 SpecA Level

Learning Objectives

By the end of this topic you will be able to:

Explain how clock speed, cores, cache size, and word length affect CPU performance

Describe pipelining and how it increases instruction throughput

Explain pipeline hazards: data, control and structural hazards

Discuss trade-offs between performance factors

Performance Factors

Clock Speed and Cores

Clock Speed (GHz)

Number of clock cycles per second. Each FDE cycle is synchronised to the clock. Higher frequency = more instructions per second. Modern CPUs: 3–5 GHz. Thermal throttling limits increase.

Number of Cores

Each core can independently execute instructions. Dual-core, quad-core, octa-core. True parallel execution across cores. Benefits depend on software being multi-threaded.

Doubling clock speed doubles performance for single-threaded workloads. Multiple cores only help if tasks can be parallelised.

Performance Factors

Cache Size and Word Length

Cache Size

Larger cache holds more frequently-used data/instructions. Reduces cache misses and main memory accesses. L1 is fastest; L3 is largest. More cache = less time waiting for RAM.

Word Length

Number of bits the CPU processes at once. A 64-bit processor processes 64 bits per instruction, handles larger numbers, addresses more memory. Wider word = more data per operation.

Modern systems are predominantly 64-bit. This allows 2⁶⁴ addressable memory locations and 64-bit integer arithmetic in a single instruction.

Pipelining

What is Pipelining?

Pipelining overlaps the execution of multiple instructions by dividing the FDE cycle into distinct stages. While one instruction is being executed, the next is being decoded and the one after is being fetched.

Cycle:   1   2   3   4   5

Instr1: [F] [D] [E]

Instr2:    [F] [D] [E]

Instr3:        [F] [D] [E]

Without pipelining: 3 instructions = 9 cycles. With pipelining: 3 instructions ≈ 5 cycles. Theoretical throughput: 1 instruction completed per cycle (after pipeline fills).

Pipeline Hazards

Data hazard: an instruction needs data that hasn't been produced yet by an earlier instruction still in the pipeline. Resolved by stalling (inserting NOPs) or forwarding.

Control hazard (branch hazard): a branch instruction changes the PC, invalidating instructions already fetched into the pipeline. Resolved by branch prediction or flushing.

Structural hazard: two instructions need the same hardware resource simultaneously (e.g. single memory bus). Resolved by duplicating resources or stalling.

Pipeline hazards cause stalls (wasted cycles). Modern CPUs use out-of-order execution and branch prediction to minimise stalls.

Exam Practice

OCR H446 Style · 4 marks

Explain what is meant by pipelining and describe one hazard that can reduce its effectiveness. State how this hazard is typically resolved.

[4 marks]

Pipelining overlaps the fetch, decode and execute stages of different instructions simultaneously.

This increases instruction throughput without increasing clock speed (up to 1 instruction per clock cycle).

Named hazard, e.g. data hazard: an instruction requires data that a preceding instruction has not yet produced.

Resolution: pipeline stall (NOP inserted) / forwarding (pass result directly to next stage) / out-of-order execution.

Common Mistakes

Don’t Lose Marks

Saying pipelining speeds up individual instructions — it does not. It increases overall throughput by executing multiple instructions in parallel stages.

Forgetting that more cores only help if software is multi-threaded. A single-threaded program runs on one core, regardless of how many cores the CPU has.

Saying increasing clock speed always improves performance — thermal limits and the memory bottleneck mean performance gains diminish at very high frequencies.

CPU Performance Factorsand Pipelining