CISC and RISC Architectures | OCR H446

Learning Objectives

By the end of this topic you will be able to:

Define CISC and RISC and describe the key characteristics of each

Compare CISC and RISC in terms of instruction set, clock cycles, registers and compiler design

Explain the advantages and disadvantages of each architecture

Give real-world examples of CISC and RISC processors

CISC

Complex Instruction Set Computer

CISC processors have a large instruction set with many complex, specialised instructions. Examples: x86 (Intel/AMD desktop CPUs).

Instructions are variable length and may take multiple clock cycles to execute.

Instructions can directly access memory (e.g. ADD mem, reg in one instruction).

Fewer registers — complex instructions handle many operations internally.

Simpler compiler design — the hardware does complex tasks so the compiler writes less code.

RISC

Reduced Instruction Set Computer

RISC processors have a small instruction set of simple instructions, each executing in exactly one clock cycle. Examples: ARM (mobile, Apple Silicon), MIPS.

Instructions are fixed length — simplifies decoding and enables efficient pipelining.

Load/store architecture: only LOAD and STORE instructions access memory. All other operations work on registers.

More registers — keeps data on-chip, reducing memory access.

More complex compiler — the compiler must break tasks into simple instructions.

Comparison

CISC vs RISC

Feature	CISC	RISC
Instruction set	Large, variable	Small, uniform
Cycles per instruction	Multiple	Single (1 cycle)
Instruction length	Variable	Fixed
Registers	Fewer	More
Memory access	Many instructions	Load/store only
Compiler complexity	Simpler	More complex
Pipelining efficiency	Harder	Easier
Example	x86, x86-64	ARM, MIPS, RISC-V

Trade-offs

Advantages and Modern Use

CISC Advantages

Single instructions do more work, reducing program size. Simpler compiler. Backwards compatibility maintained (x86 programs run on modern Intel CPUs).

RISC Advantages

Efficient pipelining — fixed 1-cycle instructions fill pipeline without stalls. Lower power consumption. More registers reduce memory traffic. Used heavily in mobile/embedded.

Modern CISC processors (x86) use RISC microarchitectures internally — complex x86 instructions are decoded into simple micro-operations (µops) that execute in a RISC-style pipeline.

Exam Practice

OCR H446 Style · 4 marks

Describe two differences between CISC and RISC processor architectures. For each difference, explain one advantage this gives to the RISC design.

[4 marks]

RISC has fixed-length instructions (CISC has variable-length). This simplifies pipelining as all instructions can be decoded uniformly.

RISC uses a load/store architecture; only LOAD and STORE access memory (CISC allows many instructions to access memory directly). ALU operations only use registers, keeping execution fast.

Award 1 mark per difference + 1 mark per advantage (max 2 differences with 2 advantages = 4 marks).

Common Mistakes

Don’t Lose Marks

Saying RISC is always faster than CISC — it depends on the task. For heavily parallelisable workloads RISC pipelines better, but CISC can complete complex operations in fewer instructions.

Saying CISC has no registers — it has registers, just fewer than RISC. Both architectures use registers; the difference is in quantity and usage patterns.

Confusing RISC compiler complexity — RISC needs a more complex compiler because the hardware is simpler. The compiler must work harder to map high-level code to simple RISC instructions.

CISC and RISCArchitectures