D-type Flip-Flops | OCR H446

Learning Objectives

By the end of this topic you will be able to:

Explain what a flip-flop is and why it is needed for memory

Describe the D-type flip-flop: inputs, outputs and behaviour

Complete timing diagrams for D-type flip-flops

Explain how flip-flops are used to build registers

Sequential Circuits

Combinational vs Sequential Logic

Combinational Logic

Output depends only on current inputs. No memory. Examples: adders, logic gates, multiplexers. Given the same inputs you always get the same output.

Sequential Logic

Output depends on current inputs AND previous state. Has memory. Examples: flip-flops, registers, counters. Can store state — essential for computer memory and CPU registers.

Computers need both: combinational logic to compute results, and sequential logic to remember state between clock cycles. The CPU uses flip-flops as the basic memory cell in registers and cache.

D-type Flip-Flop

The D-type Flip-Flop

A D-type flip-flop (Data flip-flop) has two inputs: D (Data) and CLK (Clock), and two outputs: Q and ¬Q (Q-bar). On a clock edge (typically rising edge), Q takes the value of D and holds it until the next clock edge.

Characteristic Table

D	CLK Edge	Q (next)
0	↑ Rising	0
1	↑ Rising	1
X	No edge	Q unchanged

Key Properties

• Stores 1 bit of data
• Output Q = D after each rising clock edge
• ¬Q is always the complement of Q
• Synchronised to clock — changes only at clock edges
• Used in shift registers, counters, RAM cells

Timing Diagrams

D-type Timing Diagram

Example: D input changes, Q updates on each rising CLK edge

CLK:  _|‾|_|‾|_|‾|_|‾|_

D:    0  1  1  0  1

Q:    0→0→1→1→0→0

On each rising clock edge (↑), Q captures the current value of D. Between clock edges, Q holds its value regardless of changes to D. This is called edge-triggered behaviour.

In a real processor running at 3 GHz, the clock edge occurs 3 billion times per second. Each cycle, flip-flops capture their D input, allowing registers to update synchronously across the entire CPU.

Registers

Building Registers from Flip-Flops

A register is built by connecting multiple D-type flip-flops in parallel, all sharing the same clock signal. An n-bit register uses n flip-flops and stores n bits simultaneously.

8-bit register: 8 D-type flip-flops, all clocked together. On each rising clock edge, all 8 bits are captured from the 8 D inputs and stored in Q₀–Q₇.

Shift register: flip-flops connected in series (Q of one feeds D of the next). On each clock edge, data shifts one position. Used in serial communication and for multiply/divide by 2.

The CPU's program counter, accumulator, and general-purpose registers are all built from flip-flops. SRAM (cache memory) uses flip-flops; DRAM uses capacitors (faster to write but needs refresh).

Exam Practice

OCR H446 Style · 4 marks

A D-type flip-flop starts with Q=0. The D input follows this sequence between rising clock edges: 1, 1, 0, 1, 0. Complete the Q output sequence and explain why Q does not change between clock edges.

[4 marks]

Q sequence after each rising clock edge: 0→1→1→0→1→0. On edge 1 D=1→Q=1; edge 2 D=1→Q=1; edge 3 D=0→Q=0; edge 4 D=1→Q=1; edge 5 D=0→Q=0.

Q does not change between clock edges because the D-type flip-flop is edge-triggered — it only samples the D input at the rising clock edge and holds that value until the next rising edge, regardless of changes to D in between. This synchronises all flip-flops in the circuit to the same clock.

Common Mistakes

Don't Lose Marks

Saying Q updates whenever D changes — Q only updates at the clock edge (rising or falling, depending on the flip-flop). Between clock edges Q is held at its stored value even if D changes. This is the defining characteristic of edge-triggered sequential logic.

Confusing Q and ¬Q — Q and ¬Q are always complements of each other: if Q=1 then ¬Q=0, and vice versa. They are both outputs of the flip-flop. Using Q when ¬Q is requested (or vice versa) in a timing diagram loses marks.

Saying flip-flops are only used in registers — flip-flops are also used in counters, state machines, shift registers, and as the storage cell in SRAM (cache). OCR questions may ask for multiple applications — don't limit your answer to CPU registers only.