Cambridge 9618 · International A Level Computer Science · ~14 min read
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The Memory Hierarchy
Computer systems use a hierarchy of memory types, trading off speed, cost, and capacity. As you move up the hierarchy, memory becomes faster but smaller and more expensive per byte.
CPU Registers
Fastest · Bytes · Built into CPU
↓ slower, cheaper, larger ↓
L1 Cache (SRAM)
~1-4 ns · KB · Per core
L2 Cache (SRAM)
~4-12 ns · MB · Per core or shared
Main Memory RAM (DRAM)
~50-100 ns · GB · Volatile
Secondary Storage
ms range · TB · Non-volatile
RAM (Random Access Memory)
RAM is volatile — data is lost when power is removed. It is read/write memory used to hold the currently running programs and their data.
DRAM (Dynamic RAM)
Stores each bit as a charge in a tiny capacitor
Capacitors discharge over time → must be refreshed thousands of times per second
Slower than SRAM but much cheaper and denser (more storage per area)
Used for main memory (the GB of RAM in your computer)
SRAM (Static RAM)
Stores each bit using a set of transistors (flip-flop) — no capacitor, no refresh needed
Much faster than DRAM; retains data as long as power is supplied
More complex circuit → more expensive and less dense than DRAM
Used for cache memory (L1, L2, L3)
Property
DRAM
SRAM
Technology
Capacitor + transistor (1T1C)
Flip-flop (6 transistors)
Refresh needed?
Yes — frequent refresh required
No
Speed
Slower (~50-100 ns)
Much faster (~1-4 ns)
Cost per bit
Cheaper
More expensive
Density
Higher (more storage per chip area)
Lower
Use
Main memory (RAM sticks)
CPU cache (L1, L2, L3)
ROM (Read Only Memory)
ROM is non-volatile — data is retained without power. Traditional ROM is read-only and is programmed during manufacture. It stores firmware — software permanently embedded in hardware, such as the BIOS/UEFI that starts a computer.
PROM (Programmable ROM): can be written once by the user; permanent after that
EPROM (Erasable Programmable ROM): can be erased with UV light; reprogrammable
EEPROM (Electrically Erasable Programmable ROM): erased and reprogrammed using electrical signals without removing from circuit — the basis of flash memory
Cache Memory
Cache is a small, very fast type of memory (SRAM) located between the CPU and main RAM. Its purpose is to reduce the time the CPU spends waiting for data from the slower main RAM.
Cache works by storing recently used or frequently used instructions and data. When the CPU needs data, it checks the cache first:
Cache hit — data is found in cache → fast access, no RAM access needed
Cache miss — data not in cache → CPU must fetch from RAM, data copied to cache for future use
Cache Levels
Level
Size
Speed
Location
L1 Cache
Smallest (KB)
Fastest
Directly on each CPU core
L2 Cache
Medium (MB)
Slightly slower than L1
On each core or shared
L3 Cache
Largest (MB)
Slower than L2, but faster than RAM
Shared between all cores on the chip
Why Cache Works — Locality of Reference
Temporal locality: recently accessed data is likely to be accessed again soon (e.g. loop variables)
Spatial locality: data near recently accessed data is likely to be needed soon (e.g. next instruction in sequence, adjacent array elements)
A larger cache generally reduces the miss rate — more data can be stored near the CPU. However, larger cache is more expensive and physically harder to fit close to the processor.
Exam tip: Cambridge questions on cache frequently ask you to explain why cache improves performance. Always mention: (1) cache is faster than RAM; (2) frequently used data is stored closer to the CPU; (3) this reduces the number of slow RAM accesses (fewer cache misses). Also know the SRAM vs DRAM distinction — SRAM is used for cache, DRAM for main memory.
⚠️ Common Mistakes
Saying ROM is volatile — ROM is non-volatile (data persists without power). RAM is volatile.
Saying cache is a type of secondary storage — cache is primary memory (fast, close to CPU) not secondary storage
Confusing DRAM and SRAM — DRAM needs refreshing and is used for main memory; SRAM doesn't need refreshing and is used for cache
Saying a larger cache always means better performance — a larger cache reduces miss rate but there are diminishing returns; cache size alone doesn't determine performance
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Worksheet — 1.3.5 Memory Types
8 questions · instantly marked · Cambridge 9618 standard
Q1Compare DRAM and SRAM in terms of their technology, refresh requirement, speed, and typical use.[6]
✅ Mark scheme
Mark scheme
DRAM: stores bits as charge in capacitors [1]; requires frequent refreshing [1]; slower access [1]; used for main memory [1]. SRAM: uses flip-flops (transistors) [1]; no refresh needed [1]; faster access [1]; used for cache memory [1]. Award max 6.
Q2Explain what is meant by a cache hit and a cache miss, and describe what happens in each case.[4]
✅ Mark scheme
Mark scheme
Cache hit: the required data/instruction is found in cache [1]; CPU accesses it directly from cache — no need to access slower main RAM [1]; Cache miss: required data is not in cache [1]; CPU must fetch the data from main RAM (slower); data is then copied into cache for future use [1].
Q3Explain how cache memory improves the performance of the CPU.[3]
✅ Mark scheme
Mark scheme
Cache stores frequently used instructions and data [1]; cache is faster than main RAM so accessing data from cache takes less time [1]; this reduces the number of slow accesses to main RAM, allowing the CPU to spend less time waiting for data [1].
Q4Explain the concept of temporal locality and spatial locality in the context of cache memory.[4]
✅ Mark scheme
Mark scheme
Temporal locality: if data/instruction has been recently accessed, it is likely to be accessed again soon [1]; e.g. a loop variable accessed repeatedly [1]; Spatial locality: if data at one address is accessed, data at nearby addresses is likely to be needed soon [1]; e.g. the next sequential instruction, or adjacent array elements [1].
Q5Explain the difference between RAM and ROM, giving one use of each.[4]
✅ Mark scheme
Mark scheme
RAM is volatile (data lost when power removed) and read/write [1]; used to store currently running programs and their data [1]; ROM is non-volatile (data retained without power) and originally read-only [1]; used to store firmware/BIOS — instructions needed to boot the computer [1].
Q6A multi-core processor has L1, L2, and L3 cache. Describe how these cache levels differ and why multiple levels are used.[4]
✅ Mark scheme
Mark scheme
L1: smallest and fastest, private to each core [1]; L2: larger and slightly slower, per core or shared [1]; L3: largest and slowest of the three, shared between all cores [1]; multiple levels balance cost (SRAM is expensive) with the need to reduce miss rates — if not in L1, check L2, then L3, then RAM [1].
Q7Explain what EEPROM is and why it is useful compared to traditional ROM.[3]
✅ Mark scheme
Mark scheme
EEPROM is Electrically Erasable Programmable ROM [1]; unlike traditional ROM it can be erased and reprogrammed using electrical signals without being physically removed from the circuit [1]; useful because firmware/settings can be updated while the device is in use — e.g. BIOS updates, USB configuration [1].
Q8Explain why a computer cannot rely entirely on cache memory instead of main RAM.[3]
✅ Mark scheme
Mark scheme
Cache uses SRAM which is very expensive per byte [1]; cache has a very small capacity (KB to MB) while programs and data require GB of storage [1]; it would be prohibitively expensive and physically impractical to manufacture a CPU with GB of SRAM cache [1].
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Mini Test — 1.3.5 Memory Types
10 questions · 10 marks · 10 minutes
⏱ 10:00
10 marks
Section A — Multiple Choice [5 marks]
Q1RAM is described as volatile. This means:
Q2SRAM is used for cache memory because it is:
Q3Which level of cache is closest to the CPU core and has the smallest capacity?
Q4ROM stores the BIOS because ROM is:
Q5Temporal locality means:
Section B — Short Answer [5 marks]
Q6Explain why a computer cannot use only SRAM (cache) instead of DRAM for main memory.
Mark schemeSRAM is much more expensive per byte than DRAM [1]; SRAM is also less dense (smaller storage per chip area) so GB of SRAM would be very large and costly [1].
Q7A program uses a variable i in a loop that executes 10,000 times. Explain how temporal locality relates to this.
Mark schemeTemporal locality: recently accessed data is likely to be accessed again soon [1]; the variable i is accessed in every iteration so once loaded into cache it will be a cache hit for subsequent iterations, avoiding slow RAM accesses [1].
Q8Explain what happens during a cache miss.
Mark schemeThe required data/instruction is not found in cache [1]; the CPU must access main RAM to retrieve the data, which is much slower [1]; the data is then copied into cache so future accesses will be cache hits [1]. Award 1 mark for any two correct points.
Q9State the difference between EPROM and EEPROM.
Mark schemeEPROM is erased using UV light (requires physical removal from the circuit) [1]; EEPROM is erased and reprogrammed electrically — it can be updated while in-circuit without physical removal [1].
Q10Explain why DRAM requires regular refreshing but SRAM does not.
Mark schemeDRAM stores each bit as a charge in a capacitor; capacitors naturally discharge (leak) over time [1]; so the charge must be regularly refreshed to prevent data loss [1]; SRAM uses flip-flops (transistors) which retain state as long as power is supplied and do not leak [1]. Award 1 mark for any two correct points.