3.1a CPU Architecture — Edexcel 1CP2

The CPU

The CPU (Central Processing Unit) is the brain of the computer. It carries out all processing and runs the instructions of programs.

All CPUs follow the Von Neumann architecture — stores program instructions and data in the same memory
Modern CPUs contain billions of transistors and run at billions of cycles per second (GHz)

CPU Components

Component	Function
ALU (Arithmetic Logic Unit)	Performs arithmetic (+, −, ×, ÷) and logical operations (AND, OR, NOT, comparisons)
CU (Control Unit)	Directs the operation of the processor — fetches, decodes and coordinates execution of instructions
Registers	Tiny, ultra-fast storage locations inside the CPU that hold data being processed
Cache	Small, very fast memory inside/near the CPU for frequently used data
Clock	Sends regular pulses to synchronise CPU operations — clock speed measured in GHz

Key Registers

Register	Full name	Purpose
PC	Program Counter	Holds address of next instruction to fetch
MAR	Memory Address Register	Holds address in memory being accessed
MDR	Memory Data Register	Holds data read from or written to memory
ACC	Accumulator	Holds results of ALU calculations
IR	Instruction Register	Holds the current instruction being decoded/executed

The Fetch-Decode-Execute (FDE) Cycle

The CPU constantly repeats the FDE cycle to run programs:

1. FETCH

The address in the PC is copied to the MAR. The instruction at that memory address is fetched into the MDR, then copied to the IR. The PC is incremented (increased by 1) to point to the next instruction.

2. DECODE

The CU decodes the instruction in the IR — it identifies the operation code (opcode) and any operands (data addresses). It determines what type of operation is needed.

3. EXECUTE

The appropriate component carries out the instruction. If it's arithmetic/logic, the ALU processes it and stores the result in the ACC. If it's a memory operation, data is read from or written to RAM. If it's a branch, the PC may be changed.

This cycle repeats continuously — billions of times per second — until the program ends.

The Buses

Data travels between CPU and memory via three buses:

Address bus — carries memory addresses (one direction: CPU → memory). Width = number of addressable memory locations (2ⁿ)
Data bus — carries data (bidirectional). Width = amount of data transferred at once
Control bus — carries control signals (read/write, clock signals)

Exam tip: Edexcel 1CP2 Paper 1 regularly asks you to describe each stage of the FDE cycle. Know which registers are used at each stage (PC→MAR→MDR→IR at Fetch; CU decodes IR at Decode; ALU uses ACC at Execute). Be specific — "copies address to MAR" scores more than "the CPU gets the instruction".

⚠️ Common Mistakes

Saying the PC holds the instruction — it holds the ADDRESS of the next instruction
Forgetting the PC increments during the Fetch stage
Confusing MAR (address) and MDR (data)
Saying the ALU fetches instructions — the CU controls fetching

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Worksheet — 3.1a CPU Architecture

8 Edexcel-style questions · instantly marked

Q1What is the role of the ALU in the CPU?[2]

✅ Mark scheme

The ALU performs arithmetic operations (+, −, ×, ÷) [1] and logical operations (AND, OR, NOT, comparisons) [1].

Q2State the purpose of the Program Counter (PC) register.[1]

✅ Mark scheme

The PC holds the memory address of the next instruction to be fetched [1].

Q3Describe the Fetch stage of the FDE cycle.[3]

✅ Mark scheme

Address in PC is copied to MAR [1]; instruction at that address is fetched into MDR, then copied to IR [1]; PC is incremented to point to the next instruction [1].

Q4What is the role of the Control Unit (CU)?[2]

✅ Mark scheme

The CU coordinates all CPU operations [1]; it decodes instructions and sends control signals to the relevant components [1].

Q5Explain the difference between the MAR and the MDR.[2]

✅ Mark scheme

The MAR holds the memory address of data/instruction being accessed [1]; the MDR holds the actual data or instruction read from or written to that address [1].

Q6What happens during the Decode stage of the FDE cycle?[2]

✅ Mark scheme

The CU decodes the instruction in the IR [1]; it identifies the opcode (operation) and any operands (data/addresses) [1].

Q7State the purpose of the data bus in a computer.[2]

✅ Mark scheme

The data bus transfers data between the CPU and memory (bidirectional) [1]; its width (in bits) determines how much data can be transferred at once [1].

Q8What is the Accumulator (ACC) used for?[1]

✅ Mark scheme

The ACC holds the results of calculations performed by the ALU [1].

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Term	Definition

The CPU

CPU Components

Key Registers

The Fetch-Decode-Execute (FDE) Cycle

1. FETCH

2. DECODE

3. EXECUTE

The Buses

Worksheet — 3.1a CPU Architecture

Mini Test — CPU Architecture