0100 1011
+ 1100 1110
----------
1 0001 1001 → carry out of bit 7 discarded → 0001 1001 = 25 ✓
Binary Shifts
Shifting a binary number left or right multiplies or divides by powers of 2:
Logical left shift by 1: multiply by 2. Shift all bits left, fill right with 0. MSB lost.
Logical right shift by 1: divide by 2 (integer division). Shift all bits right, fill left with 0. LSB lost.
Arithmetic right shift: preserves sign bit. Fills left with sign bit (0 for positive, 1 for negative) — maintains sign.
Logical left shift 0001 0110 (=22) by 2 positions:
0001 0110 → 0101 1000 = 88 = 22 × 4 ✓ (shifted left 2 = multiply by 2² = 4)
Exam tip: Two's complement range for n bits: −2^(n−1) to +2^(n−1)−1. For 8 bits: −128 to +127. The minimum (most negative) is 1000 0000 = −128. Zero is 0000 0000. +127 is 0111 1111.
Exam tip: To negate a two's complement number — flip all bits, add 1. This works in both directions (positive to negative AND negative to positive). Always check: +X + (−X) should give 0 (with carry discarded for 8-bit).
⚠ Common Mistakes
Forgetting that the MSB has place value −128 (not +128) in two's complement — if MSB=1, the number is negative.
Misidentifying overflow — overflow in signed arithmetic occurs only when the sign of the result is wrong (two positives add to give negative, or two negatives add to give positive). A carry out alone doesn't indicate signed overflow.
Forgetting to discard the carry when performing subtraction via two's complement — the 9th bit carry out is discarded for 8-bit arithmetic.
Q2What is the denary value of the 8-bit two's complement number 1001 0110? Show your working.[2 marks]
✓ Mark scheme
MSB = 1 → negative. −128 + 16 + 4 + 2 = −128 + 22 = −106 [2 — 1 for correct identification of negative, 1 for correct value].
Q3State the range of values that can be stored in 8-bit two's complement. What is the binary representation of the maximum and minimum values?[3 marks]
✓ Mark scheme
Range: −128 to +127 [1]; Minimum −128 = 1000 0000 [1]; Maximum +127 = 0111 1111 [1].
Q4Perform the binary addition 0110 1001 + 0011 0111. Show your working. State whether overflow has occurred in a signed 8-bit system.[4 marks]
✓ Mark scheme
0110 1001 (105) + 0011 0111 (55): column-by-column addition with carries [1]; Result = 1010 0000 [1]; In denary: 105+55=160, but 1010 0000 in two's complement = −128+32 = −96 [1]; Overflow HAS occurred — two positive numbers added to give a negative result (bit 7 changed from 0 to 1 unexpectedly) [1].
Q5Calculate 90 − 35 using 8-bit two's complement arithmetic (add the two's complement of 35 to 90). Show all steps.[4 marks]
Q6Explain what is meant by overflow in binary arithmetic, and describe when it occurs in a signed 8-bit two's complement system.[3 marks]
✓ Mark scheme
Overflow occurs when the result of an arithmetic operation is too large or too small to be represented in the allocated number of bits [1]. In 8-bit signed two's complement, overflow occurs when: two positive numbers are added and the result has a 1 in the MSB (appears negative) [1]; or two negative numbers are added and the result has a 0 in the MSB (appears positive) — indicating the result is outside the range −128 to +127 [1].
Q7Perform a logical left shift by 2 on the binary number 0001 0011. What is the result in denary? What arithmetic operation does this correspond to?[3 marks]
✓ Mark scheme
0001 0011 shifted left 2 = 0100 1100 [1] (each bit moves 2 positions left, fill with 0s from right, MSBs discarded); Denary: 64+8+4 = 76 [1]; The original 0001 0011 = 19; 19 × 4 = 76 — a logical left shift by 2 is equivalent to multiplication by 2² = 4 [1].
Q8Why is two's complement preferred over sign-magnitude for representing negative numbers in computers?[2 marks]
✓ Mark scheme
Two's complement has a single representation for zero (0000 0000), whereas sign-magnitude has both +0 (0000 0000) and −0 (1000 0000) — the same value stored two ways causes complications [1]. Two's complement allows the same hardware adder circuit to handle both addition and subtraction — subtraction is performed by adding the two's complement, requiring no separate subtraction circuit [1].
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Mini Test — 1.4.1b Two's Complement
10 questions · 10 marks · 10 minutes
5 MCQ + 5 short answer
⏱10:00
10 marks
Section A — Multiple Choice
Q1What is the denary value of the 8-bit two's complement number 1111 0000?
Q2What is the minimum value that can be stored in an 8-bit two's complement system?
Q3To calculate the two's complement of a binary number, you:
Q4A logical left shift by 1 of a binary number is equivalent to:
Q5In 8-bit signed two's complement, what binary bit pattern represents the value +127?
Section B — Short Answer
Q6Represent −30 in 8-bit two's complement. Show working.
Q8Add 0100 1100 + 0011 0101 in binary. What is the result in denary?
Mark scheme0100 1100 (76) + 0011 0101 (53) = 1000 0001. But 1000 0001 in two's complement = −127. Overflow has occurred (76+53=129, exceeds +127 max). Alternatively: result = 129 unsigned. Award marks for correct binary addition: 1000 0001 [1 mark]
Q9What is a logical right shift by 1 equivalent to mathematically?
Mark schemeDivision by 2 (integer division — any remainder/fraction is lost). Shifting right by n bits = dividing by 2ⁿ. LSB is lost. The left is filled with 0. [1 mark]
Q10Explain why two's complement is preferred over sign-magnitude for negative integers in CPUs.
Mark schemeOne zero (not two as in sign-magnitude: +0 and −0). The same adder circuit handles both addition and subtraction (subtract by adding the two's complement) — simpler hardware. Sign-magnitude requires separate addition and subtraction circuits. [1 mark for either reason]