4.7.4 Von Neumann Architecture — AQA 7517

The Stored Program Concept

The stored program concept, proposed by John von Neumann in 1945, states that both program instructions and data are stored together in the same memory (RAM) in binary form. The CPU fetches and executes instructions sequentially from this single memory. Before this, programs were "wired in" — changing a program meant rewiring hardware.

Key implications:

Programs can be modified easily (just write new values to memory)
Data and instructions share the same format (binary) and same address space
Instructions can treat other instructions as data (self-modifying code, compilers, interpreters)

Von Neumann Architecture

The Von Neumann model consists of:

CPU: ALU + Control Unit + registers
Memory Unit (RAM): stores both program and data
Input/Output devices: keyboard, monitor, etc.
System bus: data bus, address bus, control bus connecting all components

All components communicate through the single shared system bus.

Von Neumann Bottleneck

Because the CPU and memory share a single bus, data and instructions cannot be fetched simultaneously. The CPU must wait for memory — this creates the Von Neumann bottleneck: the bus limits how fast data can flow to the CPU, even if the CPU could run faster. Solutions include: cache memory, wider buses, pipelining.

Harvard Architecture

An alternative to Von Neumann. Harvard architecture has separate memory and buses for instructions and data:

Feature	Von Neumann	Harvard
Memory	Single memory for data + instructions	Separate instruction and data memory
Bus	Single shared bus	Separate buses for instruction and data
Fetch instruction + data simultaneously?	No — bottleneck	Yes — simultaneous access
Complexity	Simpler	More complex hardware
Typical use	General-purpose PCs	Embedded systems, DSPs, microcontrollers

Modified Harvard Architecture

Modern CPUs use a Modified Harvard Architecture — separate cache for instructions (instruction cache) and data (data cache), but a single unified main RAM. This gives the speed benefits of Harvard while keeping Von Neumann's flexibility and simplicity.

The Memory Hierarchy

Memory in a computer is organised in a hierarchy: faster but smaller and more expensive at the top, larger and cheaper but slower at the bottom:

Registers (fastest, tiny, inside CPU)
L1 Cache → L2 Cache → L3 Cache
RAM (main memory)
Secondary storage (HDD/SSD — slowest but largest)

Exam tip: AQA expects you to explain the stored program concept precisely — "programs and data stored in binary in the same memory." Know Von Neumann bottleneck by name. Compare Von Neumann and Harvard clearly using the table. State that modern CPUs use modified Harvard (split cache). Know the memory hierarchy in order.

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Worksheet — 4.7.4 Von Neumann Architecture

8 questions · instantly marked · AQA 7517 standard

Q1State what is meant by the 'stored program concept'.[2]

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Both program instructions and data are stored together in the same memory (RAM) in binary form [1]; the CPU fetches and executes instructions sequentially from this memory [1].

Q2List the four main components of Von Neumann architecture.[4]

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CPU (containing ALU, Control Unit, registers) [1]; Memory Unit (RAM — storing programs and data) [1]; Input/Output devices [1]; System bus (data, address, control buses) [1].

Q3Explain the Von Neumann bottleneck and state one solution to it.[3]

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Mark scheme

The Von Neumann bottleneck is the limitation caused by data and instructions sharing the same bus — the CPU cannot fetch both simultaneously and must wait for memory [1]; this limits overall performance even if the CPU could run faster [1]; solutions include: cache memory, wider buses, pipelining [1 for any one].

Q4Compare Von Neumann and Harvard architectures in terms of memory and bus structure.[4]

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Von Neumann: single shared memory for both data and instructions [1]; one shared system bus [1]. Harvard: separate memory for instructions and data [1]; separate buses for each, allowing simultaneous access [1].

Q5Give one advantage of Harvard architecture over Von Neumann.[2]

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Harvard architecture can fetch instructions and data simultaneously [1] since they use separate buses, eliminating the bottleneck [1].

Q6Explain what is meant by Modified Harvard Architecture and give an example of where it is used.[3]

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Modified Harvard uses separate caches (instruction cache + data cache) for fast access [1]; but shares a single unified main RAM [1]; used in modern general-purpose CPUs (e.g. Intel/AMD processors, ARM chips) [1].

Q7List the memory hierarchy from fastest to slowest.[3]

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Registers [1]; L1/L2/L3 cache [1]; RAM [1]; secondary storage (HDD/SSD) [1]. (3 marks for correctly ordering 4 levels.)

Q8State one implication of the stored program concept — why does it matter that programs and data are stored together?[2]

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Programs can be easily modified without rewiring hardware [1]; programs can also treat other programs or instructions as data — enabling compilers, interpreters and self-modifying code [1].

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The Stored Program Concept

Von Neumann Architecture

Von Neumann Bottleneck

Harvard Architecture

Modified Harvard Architecture

The Memory Hierarchy

Worksheet — 4.7.4 Von Neumann Architecture

Mini Test — Von Neumann Architecture