1.5.5 RISC vs CISC Architectures — Cambridge 9618

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What are RISC and CISC?

RISC and CISC are two opposing philosophies for designing a CPU's instruction set. They differ in the number, complexity, and length of instructions, and in how those instructions interact with memory and registers.

RISC — Reduced Instruction Set Computer
CISC — Complex Instruction Set Computer

🟢 RISC

Small number of simple, fixed-length instructions
Each instruction executes in exactly one clock cycle
Load/store architecture — only LOAD and STORE access memory; all other operations use registers
Many general-purpose registers
Relies on compiler to optimise code
Simpler hardware — more transistors available for other uses (e.g., cache)
Suited to pipelining
Examples: ARM, MIPS, RISC-V

🔵 CISC

Large number of complex, variable-length instructions
Instructions may take multiple clock cycles
Instructions can directly access memory (not load/store only)
Fewer general-purpose registers (complex instructions store temp values in memory)
Hardware does more work — compiler can be simpler
More complex hardware — more transistors needed for decoding
Harder to pipeline (variable-length instructions)
Examples: x86, x86-64 (Intel/AMD desktop CPUs)

RISC — Key Features in Detail

Load/Store Architecture

In RISC, only two instruction types access main memory: LOAD (memory → register) and STORE (register → memory). All arithmetic and logic operations work exclusively on values held in registers. This simplifies instruction decoding and enables faster execution.

Fixed-Length Instructions

All RISC instructions are the same size (e.g., 32 bits). This makes it easy for the CPU to fetch and decode instructions quickly and predictably — critical for pipelining.

Pipelining

Because each RISC instruction takes exactly one clock cycle and has fixed length, instructions can be pipelined efficiently. While one instruction is being executed (E), the next is being decoded (D), and the one after that is being fetched (F):

4-STAGE PIPELINE — RISC

Cycle 1:F

Cycle 2:DF

Cycle 3:EDF

Cycle 4:WEDF

F=Fetch · D=Decode · E=Execute · W=Write-back — up to 4 instructions simultaneously

CISC — Key Features in Detail

Complex Instructions

CISC processors have specialised instructions that can perform complex operations in a single instruction (e.g., multiply-and-accumulate, string copy, vector operations). A single CISC instruction might do what takes 3–10 RISC instructions.

Variable-Length Instructions

CISC instructions can be different lengths (e.g., 1 byte to 15+ bytes in x86). This means the CPU must identify instruction boundaries before decoding, which adds complexity and makes pipelining harder.

Microprogramming

CISC instructions are often implemented using microcode — each complex instruction is internally decoded into a sequence of simpler micro-operations. This adds a layer of abstraction between the instruction set and the hardware.

Comparison Table

Feature	RISC	CISC
Instruction set size	Small (typically ~100)	Large (300–500+)
Instruction length	Fixed (e.g., 32 bits)	Variable (1–15+ bytes)
Instruction complexity	Simple — each does one thing	Complex — one instruction may do many things
Clock cycles per instruction	1 cycle (typically)	Many cycles possible
Memory access	Load/store only	Many instructions access memory directly
Number of registers	Many general-purpose registers	Fewer registers
Compiler complexity	High (must use many simple instructions)	Lower (single instructions do more)
Hardware complexity	Simple (more space for cache)	Complex (large decoder/microcode unit)
Pipelining	Very well suited	Harder due to variable instruction length
Power consumption	Lower (simpler hardware)	Higher
Typical use	Mobile, embedded, tablets (ARM)	Desktop/server CPUs (Intel, AMD)
Examples	ARM (phones, Raspberry Pi), RISC-V	x86-64 (Intel Core, AMD Ryzen)

Modern Reality

Modern x86 CISC processors internally translate their complex variable-length instructions into RISC-like micro-operations before executing them. This means the two architectures have converged somewhat at the implementation level, even though the instruction set architecture (ISA) remains different.

ARM (RISC) dominates mobile and embedded devices due to its lower power consumption. x86-64 (CISC) dominates desktop and server computing due to its large ecosystem of software.

Exam tip: Cambridge 9618 commonly asks you to "compare RISC and CISC" — state features as opposing pairs: RISC has fewer, simpler, fixed-length instructions vs CISC has many, complex, variable-length instructions; RISC uses load/store architecture vs CISC can access memory directly; RISC is better suited to pipelining vs CISC harder to pipeline. Give two sides for each mark.

⚠️ Common Mistakes

Saying RISC is "better" than CISC — both have use cases. RISC dominates mobile; CISC dominates desktops. Never say one is universally better.
Confusing "fewer instructions" with "faster programs" — a RISC program may need many more instructions to do the same task as one CISC instruction; but each RISC instruction is faster to decode/execute
Forgetting the load/store rule — in RISC, ONLY load and store instructions access memory. All arithmetic uses registers.
Saying RISC is cheaper — this depends on context. RISC chips are often smaller and consume less power, which reduces cost in mobile; but CISC dominates where backward-compatibility matters.

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Worksheet — 1.5.5 RISC vs CISC

6 questions · instantly marked · Cambridge 9618 standard

Q1State three differences between RISC and CISC processor architectures.[3]

✅ Mark scheme

Any three: RISC has fewer/simpler instructions vs CISC has many/complex instructions [1]; RISC instructions are fixed-length vs CISC instructions are variable-length [1]; RISC uses load/store architecture only vs CISC instructions can directly access memory [1]; RISC executes each instruction in one cycle vs CISC may take multiple cycles [1]; RISC has more registers vs CISC has fewer [1].

Q2Explain what is meant by a "load/store architecture" in RISC processors.[2]

✅ Mark scheme

Only LOAD and STORE instructions access main memory [1]; all other instructions (arithmetic, logic) operate only on data held in registers [1].

Q3Explain why RISC processors are better suited to pipelining than CISC processors.[3]

✅ Mark scheme

RISC instructions are fixed-length, making it easy to identify instruction boundaries and fetch the next instruction while the current one executes [1]; RISC instructions each take one clock cycle, so stages of different instructions can overlap precisely [1]; CISC variable-length instructions mean the CPU must determine instruction boundaries before decoding, disrupting pipeline flow [1].

Q4Give one advantage and one disadvantage of CISC having complex instructions that can access memory directly.[2]

✅ Mark scheme

Advantage: programmers/compilers can write programs with fewer instructions (one instruction does more work) [1]; Disadvantage: instructions take multiple clock cycles, making execution slower and pipelining harder [1].

Q5ARM processors (RISC) are used in smartphones rather than x86 CISC processors. Give two reasons why RISC is preferred for mobile devices.[2]

✅ Mark scheme

Any two: simpler hardware uses less power — extends battery life [1]; smaller chip size possible — better for compact devices [1]; lower heat generation — suitable for devices without fans/heatsinks [1].

Q6Modern x86 CISC processors internally convert instructions to micro-operations. Explain how this relates to the RISC vs CISC debate.[3]

✅ Mark scheme

The x86 instruction set (CISC) is presented to programmers and compilers as complex variable-length instructions [1]; internally, the CPU's decoder breaks each complex instruction into simple fixed-length RISC-like micro-operations [1]; these micro-operations are then pipelined and executed efficiently, combining the software compatibility of CISC with some execution advantages of RISC [1].

Q7Compare the instruction set design philosophies of RISC and CISC architectures. Explain why RISC processors are generally more suitable for pipelined execution than CISC processors.[5]

✅ Mark scheme

RISC: small set of simple, fixed-length instructions each executing in one clock cycle — 1 mark; CISC: large set of complex, variable-length instructions that may take multiple clock cycles — 1 mark; RISC pipelines efficiently because all instructions are the same length and take the same number of cycles — easy to fetch, decode, execute simultaneously — 1 mark; CISC causes pipeline hazards because variable instruction lengths make it hard to predict where the next instruction starts — 1 mark; RISC uses more registers so fewer memory accesses during computation — 1 mark.

Q8Explain what is meant by a load/store architecture used in RISC processors. Describe the sequence of instructions a RISC processor would need to add the values stored at two memory addresses and store the result back in memory.[4]

✅ Mark scheme

Load/store: arithmetic operations can only be performed on data in registers, not directly on memory — 1 mark; to add memory values: LOAD R1, address1 — load first value into register — 1 mark; LOAD R2, address2 — load second value — 1 mark; ADD R3, R1, R2 — add registers; STORE R3, address3 — store result back to memory — 1 mark.

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Term	Definition

What are RISC and CISC?

RISC — Key Features in Detail

Load/Store Architecture

Fixed-Length Instructions

Pipelining

CISC — Key Features in Detail

Complex Instructions

Variable-Length Instructions

Microprogramming

Comparison Table

Modern Reality

Worksheet — 1.5.5 RISC vs CISC

Mini Test — 1.5.5 RISC vs CISC