Cambridge 9618 · International A Level Computer Science · ~22 min read
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RISC vs CISC
Processor architectures differ in how their instruction sets are designed. The two main approaches are RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer).
⚡ RISC
Small set of simple instructions
Each instruction executes in one clock cycle
Load/store architecture — only LOAD and STORE access memory; all other operations use registers
More general-purpose registers
Simple hardware — no microcode
Compiler generates efficient sequences of simple instructions
Supports pipelining very well
Used in: ARM processors (phones, tablets, Apple M-series)
🏗️ CISC
Large set of complex instructions
Instructions may take multiple clock cycles
Many instructions can access memory directly (not just LOAD/STORE)
Fewer general-purpose registers
More complex hardware — uses microcode to decode complex instructions
Compiler writes fewer, more powerful instructions
Harder to pipeline due to variable instruction length/timing
Used in: x86 processors (Intel/AMD — desktop/laptop CPUs)
Feature
RISC
CISC
Instruction set size
Small (~100 instructions)
Large (hundreds of instructions)
Instruction length
Fixed (same size)
Variable (different sizes)
Clock cycles per instruction
1
Variable (1 to many)
Memory access
LOAD/STORE only
Many instructions access memory
Registers
Many
Fewer
Microcode
No
Often yes (to decode complex instructions)
Code size
Larger (more instructions needed)
Smaller (single instruction does more)
Examples
ARM, MIPS, RISC-V
Intel x86, AMD64
Pipelining
Pipelining is a technique that increases the throughput (instructions per second) of a processor by executing multiple instructions simultaneously, each at a different stage. Without pipelining, each instruction must complete all stages before the next begins. With pipelining, stages overlap.
FDE cycle stages
STAGE 1
Fetch
PC → MAR, instruction fetched from memory to MDR, MDR → CIR, PC incremented
STAGE 2
Decode
Control unit decodes opcode and identifies operands/addressing mode
STAGE 3
Execute
ALU performs operation (arithmetic, logic, memory read/write, branch)
STAGE 4
Write Back
Result stored to register or memory
Pipelined execution — visualised
Without pipelining, 4 instructions take 16 clock cycles (4 stages × 4 instructions). With pipelining, the same 4 instructions take only 7 cycles because stages overlap:
Key insight: at cycle 4, all four pipeline stages are busy simultaneously — Instruction 1 is writing back, Instruction 2 is executing, Instruction 3 is decoding, Instruction 4 is being fetched. This gives near-4× throughput improvement for 4 stages.
Pipeline Hazards
Pipelining doesn't always work perfectly. Three types of hazard can stall the pipeline:
Data Hazard
An instruction needs the result of a previous instruction that hasn't finished yet. E.g. Instruction 2 needs a value that Instruction 1 is still computing. Solution: pipeline stall (bubble inserted), forwarding/bypassing.
Control Hazard (Branch Hazard)
A branch instruction changes the program counter — the processor doesn't know which instruction to fetch next until the branch is resolved. Solution: branch prediction (guess which path and prefetch — flush pipeline if wrong), delayed branching.
Structural Hazard
Two instructions need the same hardware resource at the same time. E.g. both need to access memory simultaneously. Solution: duplicate resources (separate instruction/data caches), pipeline stall.
Parallel Processing
Parallel processing uses multiple processors or processor cores to execute different parts of a task simultaneously, reducing overall completion time.
📊
SIMD — Single Instruction, Multiple Data
One instruction applied to multiple data items simultaneously. Used in graphics, audio, scientific computing. E.g. "multiply all these values by 2" applied to 8 numbers at once using a vector/SIMD unit.
🖥️
MIMD — Multiple Instructions, Multiple Data
Different processors execute different instructions on different data simultaneously. Used in multi-core CPUs, distributed computing, server farms. Most flexible and common parallel architecture.
⚡
Multi-core CPUs
Multiple processor cores on one chip. Each core can fetch, decode, and execute independently. Quad-core = 4 cores, each potentially handling a different process. Modern phones and laptops have 4–16 cores.
🌐
Massively Parallel
Thousands of processors (GPUs have thousands of cores). Used for: machine learning training, weather simulation, physics rendering, cryptocurrency mining. GPU cores are simpler than CPU cores but there are far more of them.
Limitations of parallel processing
Amdahl's Law: the speedup from parallel processing is limited by the sequential (non-parallelisable) portion of the program. If 20% must be sequential, max speedup = 5× regardless of cores
Communication overhead: processors must share data — coordination time can reduce gains
Not all tasks are parallelisable — some algorithms are inherently sequential
Cambridge 9618 exam tip: Know 4 key RISC properties: simple instructions, fixed length, one cycle per instruction, load/store only. Know CISC: complex/variable instructions, multiple cycles, direct memory access. For pipelining: draw the grid (F/D/E/W stages overlapping), know the three hazards (data, control, structural) and a solution for each. For parallel processing: SIMD = one instruction many data (graphics); MIMD = different instructions different data (multi-core). Know Amdahl's Law concept (sequential bottleneck limits speedup).
⚠️ Common Mistakes
Saying RISC is "faster" than CISC in all cases — RISC executes each instruction faster but may need more instructions per task; modern CISC CPUs use many RISC-like micro-ops internally
Confusing pipelining with parallel processing — pipelining overlaps stages of sequential instructions in ONE pipeline; parallel processing runs truly simultaneous tasks on multiple processors
Forgetting that hazards can stall the pipeline — it doesn't always achieve full throughput; a control hazard after a branch instruction may flush several pipeline stages
Saying more cores always means faster execution — Amdahl's Law: if even 20% of code is sequential, adding infinite cores gives only 5× speedup at best
Confusing SIMD and MIMD — SIMD: ONE instruction on MANY data items (GPU shader); MIMD: MANY instructions on MANY data items (multi-core CPU)
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Worksheet — 3.3.1 Processors
8 questions · Cambridge 9618 standard
Q1State four characteristics of a RISC processor that differ from CISC.[4]
✅ Mark scheme
Any four from: small set of simple instructions [1]; fixed-length instructions [1]; each instruction executes in one clock cycle [1]; load/store architecture — only LOAD and STORE access memory, other operations use registers [1]; more general-purpose registers [1]; no microcode / simpler hardware [1].
Q2Explain what pipelining is and how it improves processor performance. Use an example with at least 3 instructions.[4]
✅ Mark scheme
Pipelining divides instruction execution into separate stages (fetch, decode, execute, write back) [1]; while one instruction is being executed, the next is being decoded, and a third is being fetched simultaneously [1]; example: by cycle 4, instruction 1 is writing back, instruction 2 executing, instruction 3 decoding, instruction 4 fetching [1]; this increases instruction throughput (more instructions completed per second) without increasing clock speed [1].
Q3Describe a data hazard in pipelining and state one solution.[3]
✅ Mark scheme
A data hazard occurs when an instruction needs data that a previous instruction has not yet computed/written back [1]; e.g. if instruction 2 needs the result of instruction 1 which is still in the execute stage, instruction 2 cannot proceed correctly [1]; solution: pipeline stall — insert a "bubble" (NOP) to delay instruction 2 until the result is ready; or forwarding/bypassing — pass the result directly from the execute stage output to the next instruction without waiting for write-back [1].
Q4Distinguish between SIMD and MIMD parallel processing and give a real-world application of each.[4]
✅ Mark scheme
SIMD: a single instruction is applied to multiple data items simultaneously [1]; application: graphics rendering — the same shader operation applied to thousands of pixels at once [1]; MIMD: different processors execute different instructions on different data simultaneously [1]; application: multi-core CPU running multiple processes (one core running a browser, another running a word processor) [1].
Q5A program is 75% parallelisable. Using Amdahl's Law concept, explain why doubling the number of processors does not double the speed.[3]
✅ Mark scheme
The remaining 25% of the program is sequential and cannot be parallelised — it must run on a single processor [1]; with 2 processors, the 75% parallel portion takes half the time, but the 25% sequential portion takes the same time [1]; total speedup = 1 / (0.25 + 0.75/2) = 1/0.625 = 1.6× — significantly less than the theoretical 2× speedup; adding more processors still cannot speed up the sequential portion [1].
Q6Explain why RISC processors are generally easier to pipeline than CISC processors.[3]
✅ Mark scheme
RISC instructions are all the same fixed length, so the fetch stage always retrieves exactly one instruction — no ambiguity about where each instruction starts [1]; RISC instructions each take exactly one clock cycle to execute — so all pipeline stages take the same time and the pipeline flows evenly [1]; CISC instructions are variable length and take variable numbers of cycles — this creates timing mismatches between stages and makes it harder to keep the pipeline moving without stalls [1].
Q7Explain the difference between SIMD (Single Instruction Multiple Data) and MIMD (Multiple Instruction Multiple Data) parallel processing. Give one real-world application of each, explaining why that application benefits from the specific type of parallelism it uses.[5]
✅ Mark scheme
SIMD: the same instruction is applied simultaneously to multiple data elements [1]; MIMD: multiple processors each execute different instructions on different data simultaneously [1]; SIMD application: GPU rendering — each shader core applies the same lighting/colour calculation to thousands of pixels simultaneously, exploiting data-level parallelism [1]; MIMD application: multi-core CPU running a web server — each core handles a different HTTP request (different instructions, different data) simultaneously [1]; Award 1 mark for clear link between application and why it suits that parallelism type [1].
Q8State two benefits and one limitation of parallel processing. Explain what Amdahl's Law states about the theoretical speedup achievable by adding more processors to a task that is only partially parallelisable.[5]
✅ Mark scheme
Benefit 1: faster execution of tasks that can be divided into independent subtasks [1]; Benefit 2: allows tackling larger problems (e.g. scientific simulations) that would take too long on a single processor [1]; Limitation: not all problems are parallelisable — sequential dependencies mean some portions must execute in order [1]; Amdahl's Law: speedup = 1 / (S + P/N) where S is the serial fraction, P is the parallel fraction (P = 1−S), N is number of processors [1]; even with an infinite number of processors, the maximum speedup is bounded by 1/S — the serial portion of the task sets an upper limit that cannot be overcome by adding more processors [1].
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Mini Test — 3.3.1 Processors
10 questions · 10 marks · 10 minutes
⏱ 10:00
Section A — Multiple Choice [5 marks]
Q1In a RISC processor, which types of instruction can access main memory?
Q2What type of hazard occurs when a branch instruction causes uncertainty about which instruction to fetch next?
Q3ARM processors (used in smartphones) use which architecture?
Q4SIMD parallel processing applies:
Q5Pipelining increases which aspect of processor performance?
Section B — Short Answer [5 marks]
Q6State two differences between RISC and CISC instruction sets.
Mark schemeAny two from: RISC has a small/simple instruction set; CISC has many complex instructions [1]; RISC instructions are fixed length; CISC are variable length [1]; RISC: one clock cycle per instruction; CISC: variable clock cycles [1]; RISC: load/store only accesses memory; CISC: many instructions can access memory directly [1].
Q7Describe how pipelining works using the Fetch-Decode-Execute cycle.
Mark schemeInstruction execution is divided into separate stages: Fetch, Decode, Execute (and Write Back) [1]; while instruction 1 is in the Execute stage, instruction 2 is being Decoded and instruction 3 is being Fetched simultaneously [1]; multiple instructions are in progress at different stages at the same time, increasing throughput without increasing clock speed [1].
Q8State what a structural hazard is and give one solution.
Mark schemeA structural hazard occurs when two instructions in the pipeline need the same hardware resource (e.g. memory) at the same time [1]; solution: duplicate the resource — e.g. use separate instruction cache and data cache so fetch and memory access can happen simultaneously; or insert a pipeline stall to delay one instruction [1].
Q9State what Amdahl's Law tells us about parallel processing.
Mark schemeAmdahl's Law states that the maximum speedup achievable from parallel processing is limited by the sequential (non-parallelisable) portion of the program [1]; even with an infinite number of processors, the speedup cannot exceed 1/(fraction that must be sequential) — the sequential bottleneck always limits overall performance [1].
Q10Give one advantage of having more registers in a RISC processor compared to CISC.
Mark schemeWith more registers, the processor can keep more intermediate values stored locally without needing to access main memory [1]; since memory accesses are much slower than register accesses, this reduces the number of LOAD/STORE operations needed and improves overall execution speed [1].