OCR H446 · A Level Computer Science · ~15 min read
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Half Adder
A half adder adds two single binary bits (A and B) and produces two outputs: Sum (S) and Carry (C). It cannot accept a carry-in from a previous stage.
A
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Sum (S)
Carry (C)
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S = A XOR B (A ⊕ B) C = A AND B (A · B)
Implementation: one XOR gate (for Sum) and one AND gate (for Carry).
Full Adder
A full adder adds three bits: A, B, and a carry-in (Cᵢₙ) from a previous stage. It produces Sum (S) and carry-out (Cout).
A
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Cᵢₙ
Sum (S)
Cₒᵤₜ
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S = A ⊕ B ⊕ Cᵢₙ Cₒᵤₜ = (A · B) + (Cᵢₙ · (A ⊕ B))
Implementation: two XOR gates, two AND gates, one OR gate. Or equivalently: two half adders plus an OR gate.
Ripple-Carry Adder
To add multi-bit binary numbers, full adders are chained: the carry-out of each bit position becomes the carry-in of the next. This is called a ripple-carry adder.
For an 8-bit ripple-carry adder: the carry "ripples" from bit 0 (LSB) through to bit 7 (MSB). The carry-out of the MSB stage is the overflow flag (or forms the 9th bit of the result).
Bit 0: Half Adder — A₀ + B₀ → S₀, C₀ Bit 1: Full Adder — A₁ + B₁ + C₀ → S₁, C₁ Bit 2: Full Adder — A₂ + B₂ + C₁ → S₂, C₂ ... Bit n: Full Adder — Aₙ + Bₙ + Cₙ₋₁ → Sₙ, Cₙ
Limitation: Ripple-carry is slow for wide operands — the carry must propagate through every bit stage serially before the final result is valid. Modern CPUs use faster architectures like carry-lookahead adders, but ripple-carry is simpler to understand and implement.
The Arithmetic Logic Unit (ALU)
The ALU is the component of the CPU that performs all arithmetic and logical operations. It is the computational heart of the processor.
Arithmetic Operations
Addition (A + B)
Subtraction (A − B, implemented as addition of two's complement)
Increment (A + 1), Decrement (A − 1)
Multiplication (via repeated addition or hardware multiplier)
Bit shifts: logical shift left/right, arithmetic shift, rotate
Comparison operations (to set condition flags)
ALU Inputs and Outputs
Signal
Direction
Description
Operand A
Input
First operand (from accumulator or register)
Operand B
Input
Second operand (from register or immediate)
Opcode / Control
Input
Selects the operation to perform (e.g. ADD, AND)
Carry-in
Input
Carry from a previous operation (for multi-word arithmetic)
Result
Output
Computed result sent to a register
Status Flags
Output
Condition codes: Zero (Z), Negative (N), Carry (C), Overflow (V)
Status Flags
The ALU sets flags in the status register (flags register) after each operation:
Zero (Z): Result is all zeros — used for equality comparisons (BEQ branch)
Negative (N): MSB of result is 1 — result is negative in two's complement
Carry (C): An unsigned carry out of the MSB — indicates unsigned overflow
Overflow (V): Signed overflow — result doesn't fit in the word size (e.g. adding two positives gives negative)
These flags are used by conditional branch instructions to make decisions (e.g. jump if zero, jump if carry).
Exam tip: Know the half adder equations (S=A XOR B, C=A AND B) and the full adder truth table. Be able to state the difference: half adder has no carry-in, full adder does. For the ALU, know the four main status flags and what they each indicate.
Exam tip: Subtraction is typically implemented as addition of the two's complement. A − B = A + (¬B + 1). The ALU just complements operand B and sets carry-in to 1 to achieve subtraction with the same adder circuit — no separate subtraction hardware needed.
⚠ Common Mistakes
Confusing carry and overflow: Carry is for unsigned arithmetic (an extra bit beyond the word width); Overflow is for signed arithmetic (the sign bit is wrong).
Half adder vs full adder: A half adder adds 2 bits with no carry-in. A full adder adds 3 bits (A + B + Cin). Only full adders can be chained to form a multi-bit adder (except the first stage, which can be a half adder).
The ripple-carry adder's first stage: Bit 0 uses a half adder (no previous carry-in) or a full adder with Cin = 0.
Thinking the ALU only does arithmetic: it also performs all logical bitwise operations (AND, OR, XOR, NOT, shifts).
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Worksheet — 1.4.3d Adders and the ALU
8 questions · 23 marks · instantly marked
Q1State the two outputs of a half adder and write the Boolean expression for each.[4 marks]
✓ Mark scheme
Output 1: Sum (S) = A XOR B = A ⊕ B [1]. Output 2: Carry (C) = A AND B = A · B [1]. One mark each for naming the output [1] and giving the correct Boolean expression [1]. Sum uses XOR because 1+1 in binary gives 0 (with carry), which XOR models. Carry uses AND because carry only occurs when both A and B are 1.
Q2Explain the difference between a half adder and a full adder.[3 marks]
✓ Mark scheme
A half adder adds two bits (A and B) only — it has no carry-in input [1]. A full adder adds three bits (A, B, and a carry-in Cᵢₙ) and produces a Sum and a carry-out [1]. A full adder is needed to chain multiple adders together into a multi-bit (ripple-carry) adder because each stage must accept the carry from the previous stage [1].
Q3Complete the truth table for a full adder for the input combinations: A=1, B=1, Cin=0 and A=1, B=1, Cin=1.[4 marks]
✓ Mark scheme
A=1, B=1, Cin=0: S=0, Cout=1 [2]. Explanation: 1+1+0=2 in decimal = 10 in binary → Sum=0, Carry=1. A=1, B=1, Cin=1: S=1, Cout=1 [2]. Explanation: 1+1+1=3 in decimal = 11 in binary → Sum=1, Carry=1. (1 mark per output per row)
Q4Explain what a ripple-carry adder is and state one limitation of this design.[3 marks]
✓ Mark scheme
A ripple-carry adder chains multiple full adders together, where the carry-out of each stage becomes the carry-in of the next [1]. This allows multi-bit binary addition (e.g. 8-bit, 16-bit) [1]. Limitation: it is slow because the carry must propagate serially through each bit stage before the final result is valid — for wide operands (e.g. 64-bit) this causes significant delays [1].
Q5State four different types of operations the ALU can perform. Give one example of each type.[4 marks]
✓ Mark scheme
1 mark each for any four: Arithmetic — e.g. addition (A + B) or subtraction [1]. Logical bitwise — e.g. AND, OR, XOR, NOT [1]. Comparison — e.g. compare two values, set flags [1]. Shift/rotate — e.g. logical shift left (multiply by 2), arithmetic right shift [1]. (Other valid: increment, decrement, multiply, divide)
Q6Name the four main status flags the ALU produces. For each, describe when it is set to 1.[4 marks]
✓ Mark scheme
Zero (Z): set when result is zero — all bits 0 [1]. Negative (N): set when MSB of result is 1, indicating a negative result in two's complement [1]. Carry (C): set when there is an unsigned carry-out beyond the word width — indicates unsigned overflow [1]. Overflow (V): set when a signed arithmetic overflow occurs — e.g. adding two positive numbers gives a negative result [1]. (1 mark each — name + when set)
Q7Explain how the ALU performs subtraction (A − B) using addition hardware. What is the advantage of this approach?[3 marks]
✓ Mark scheme
A − B is computed as A + (−B) = A + (¬B + 1) (adding the two's complement of B) [1]. The ALU inverts/complements all bits of B (¬B) and sets the carry-in to 1 (to add 1), then feeds this through the standard adder [1]. Advantage: no separate subtraction circuit is needed — the same adder hardware performs both addition and subtraction, reducing chip area and complexity [1].
Q8Distinguish between a carry flag and an overflow flag. Give an example of when each would be set.[4 marks]
✓ Mark scheme
Carry flag: set when unsigned arithmetic produces a result that exceeds the word width — extra bit carry-out beyond MSB [1]. Example: 8-bit: 255+1=256, which overflows 8 bits → carry flag set [1]. Overflow flag: set when signed arithmetic produces an incorrect result — the sign bit is wrong [1]. Example: 8-bit signed: 127+1=−128 (sign bit flips incorrectly) → overflow flag set [1]. (Key distinction: carry=unsigned overflow; overflow=signed overflow)
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Mini Test — 1.4.3d Adders & ALU
10 questions · 10 marks · 10 minutes
5 MCQ + 5 short answer
⏱10:00
10 marks
Section A — Multiple Choice
Q1What is the Sum output of a half adder when A=1 and B=1?
Q2Which gate implements the Sum output of a half adder?
Q3What does the Zero (Z) flag in the ALU status register indicate?
Q4How many inputs does a full adder have?
Q5In a ripple-carry adder, what connects each full adder stage to the next?
Section B — Short Answer
Q6What are the two Boolean expressions for the outputs of a half adder?
Mark schemeSum S = A XOR B (A ⊕ B) and Carry C = A AND B (A · B). Sum uses XOR because 1⊕1=0 (with carry); AND gives carry only when both inputs are 1. [1 mark]
Q7Why can a half adder not be used for all stages of a multi-bit adder?
Mark schemeA half adder has no carry-in input. Multi-bit adders need each stage to accept a carry from the previous stage. Only full adders (with Cin input) can be chained to propagate the carry between bit positions. [1 mark]
Q8State the difference between the Carry flag and the Overflow flag.
Mark schemeCarry flag: set for unsigned arithmetic overflow (result exceeds word width — a carry out of the MSB). Overflow flag: set for signed arithmetic overflow (result has the wrong sign — cannot be correctly represented in two's complement). [1 mark]
Q9State the full adder output for A=0, B=1, Cin=1.
Mark scheme0 + 1 + 1 = 2 in decimal = 10 in binary. Sum S = 0, Carry-out Cout = 1. Check: S = 0⊕1⊕1 = 0; Cout = (0·1) + (1·(0⊕1)) = 0 + (1·1) = 1. [1 mark]
Q10Give two types of operations performed by the ALU (other than addition).
Mark schemeAny two of: Subtraction, logical AND/OR/XOR/NOT (bitwise), bit shifts (logical or arithmetic), comparison (set flags), increment/decrement, multiplication/division. [1 mark for any two correct]