Sequential Logic and Memory

The logic gates studied so far are combinational — the output depends only on the current inputs. Sequential logic circuits have outputs that depend on both current inputs AND the circuit's past state (memory). Flip-flops are the fundamental building blocks of sequential logic.

A flip-flop is a bistable circuit — it has two stable states (0 and 1) and can store one bit of information. It retains its state until a clock pulse or input causes it to change.

The D-type Flip-Flop

The D-type flip-flop (Data flip-flop or Delay flip-flop) is the most commonly examined sequential circuit at A Level. It has:

• D (Data/Input): The data bit to be stored
• CLK (Clock): Triggers when the flip-flop samples D
• Q (Output): The stored bit — the flip-flop's current state
• Q̄ (Complement Output): Always the inverse of Q (not always shown in exam questions)

Behaviour: On the rising edge of the clock signal (0→1 transition), the flip-flop copies the value of D to Q. Between clock edges, Q holds its last value regardless of changes in D.

Characteristic Table (Truth Table)

The key equation: Q(next) = D — the output simply follows the input, but only at the clock edge.

Timing Diagram

This timing diagram shows how Q responds to D and CLK (rising-edge triggered):

Key observations from the timing diagram:

• Q changes value only on the rising edge of CLK (indicated by ↑)
• If D=1 at the rising edge → Q becomes 1
• If D=0 at the rising edge → Q becomes 0
• Changes in D between clock edges have no effect on Q

Edge Triggering vs Level Triggering

The D-type flip-flop is edge-triggered — it responds only at the moment of a clock edge (rising or falling). This is in contrast to a latch which is level-triggered (responds whenever the enable signal is high). Edge triggering is more precise and eliminates timing hazards.

• Rising-edge triggered: Q updates at CLK 0→1 transition (most common in exams)
• Falling-edge triggered: Q updates at CLK 1→0 transition

Applications of D-type Flip-Flops

1. Registers

A single D-type flip-flop stores 1 bit. An 8-bit register is built from 8 D-type flip-flops sharing the same clock, each holding one bit. The CPU's general-purpose registers, accumulator, program counter, and status register are all built from flip-flops.

2. Counters

D-type flip-flops can be connected in series (with Q̄ fed back to D) to form a binary counter. Each flip-flop divides the clock frequency by 2. A chain of n flip-flops forms an n-bit counter (0 to 2ⁿ−1).

3. Shift Registers

Chaining flip-flops so that the Q output of one feeds the D input of the next creates a shift register. Data moves along the chain one position per clock cycle. Used in serial-to-parallel and parallel-to-serial conversion (e.g. USB to internal bus).

4. Memory Elements

Static RAM (SRAM) cells are built from flip-flop circuits. Each bit of cache memory or a CPU register corresponds to one flip-flop.

Synchronous vs Asynchronous Circuits

When all flip-flops in a circuit share the same clock signal, the circuit is synchronous — all state changes occur simultaneously at each clock edge. This is the standard in modern digital design. An asynchronous circuit has no shared clock — components change state as soon as their inputs change, which can cause timing hazards (glitches).