AQA 7517 · A-Level Computer Science · ~15 min read
The Processor
The Central Processing Unit (CPU) is the main processing component of a computer. It fetches, decodes and executes instructions. The processor contains several key components:
ALU (Arithmetic Logic Unit): performs arithmetic (+, −, ×, ÷) and logical operations (AND, OR, NOT, comparisons)
Control Unit (CU): fetches and decodes instructions, controls and coordinates all components, generates control signals
Registers: extremely fast, small storage locations inside the CPU — hold data currently being processed
Cache: small, fast memory between CPU and RAM — reduces fetch time
Key Registers (AQA Required)
Register
Purpose
PC (Program Counter)
Holds address of next instruction to fetch
MAR (Memory Address Register)
Holds address to be read from / written to in memory
MDR (Memory Data Register)
Holds data read from or to be written to memory
CIR (Current Instruction Register)
Holds the current instruction being decoded and executed
Accumulator (ACC)
Holds the result of ALU operations
The Fetch-Decode-Execute (FDE) Cycle
The CPU continuously repeats this three-stage cycle:
Fetch: address from PC → MAR; instruction loaded from RAM → MDR → CIR; PC incremented
Decode: CU decodes instruction in CIR into opcode (what to do) and operand (data/address)
Execute: CU carries out the instruction — ALU performs calculation, or data is moved, or jump occurs
Cache Memory
Cache sits between CPU and RAM. Frequently accessed data is stored there so the CPU doesn't wait for slower RAM. Cache is organised in levels:
L1 cache: smallest, fastest, inside the CPU core (typically 32–64 KB)
L3 cache: shared between cores, larger still (typically 4–32 MB)
Buses
Data travels between components via buses (groups of parallel wires):
Data bus: carries actual data; bidirectional
Address bus: carries memory addresses from CPU to RAM; unidirectional (CPU → RAM)
Control bus: carries control signals (read/write, clock); bidirectional
The width of the address bus determines how much RAM can be addressed (32-bit → 4 GB; 64-bit → vast amounts). The width of the data bus determines how much data moves per cycle.
CPU Performance Factors
Clock speed: measured in GHz — number of FDE cycles per second; higher = faster
Number of cores: multi-core CPUs can process multiple instructions simultaneously
Exam tip: Know all five registers (PC, MAR, MDR, CIR, ACC) and their roles. Describe the FDE cycle precisely — examiners expect the detail of PC→MAR and PC incrementing during Fetch. Know the three buses, their widths, and what bus width affects. Know L1/L2/L3 cache. Explain performance factors: clock speed, cores, cache size.
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Worksheet — 4.7.1 Internal Hardware
8 questions · instantly marked · AQA 7517 standard
Q1State the role of the ALU in a CPU.[2]
✅ Mark scheme
Mark scheme
The ALU performs arithmetic operations (addition, subtraction, multiplication, division) [1] and logical operations (AND, OR, NOT, comparisons) [1].
Q2Describe the role of the Program Counter (PC) in the Fetch-Decode-Execute cycle.[2]
✅ Mark scheme
Mark scheme
The PC holds the memory address of the next instruction to be fetched [1]; after fetching, the PC is automatically incremented to point to the next instruction [1].
Q3Describe the Fetch stage of the FDE cycle in detail, naming the registers involved.[4]
✅ Mark scheme
Mark scheme
Address in PC is copied to MAR [1]; memory at that address is read and data placed in MDR [1]; data (instruction) is copied from MDR to CIR [1]; PC is incremented to hold the address of the next instruction [1].
Q4Explain what the width of the address bus determines, and give an example for a 32-bit address bus.[3]
✅ Mark scheme
Mark scheme
The width of the address bus determines the maximum amount of RAM that can be directly addressed [1]; a 32-bit address bus can address 2³² = 4,294,967,296 memory locations [1]; this is approximately 4 GB of RAM [1].
Q5What is the difference between L1 and L3 cache in a CPU?[3]
✅ Mark scheme
Mark scheme
L1 is the smallest and fastest cache, located closest to the CPU core [1]; L3 is larger (several MB) but slower, and typically shared between all cores [1]; L1 stores the most frequently accessed data since it is fastest; L3 acts as a larger fallback before accessing RAM [1].
Q6State the direction(s) of data flow for each of the three buses (data, address, control).[3]
✅ Mark scheme
Mark scheme
Data bus: bidirectional — data flows both to and from the CPU [1]; address bus: unidirectional — addresses are sent from the CPU to memory [1]; control bus: bidirectional — carries control signals in both directions [1].
Q7Explain how increasing the number of cores can improve CPU performance. Give one limitation.[3]
✅ Mark scheme
Mark scheme
More cores allow multiple instructions/threads to execute simultaneously (parallel processing) [1]; this improves performance for multi-threaded tasks such as video rendering or running multiple applications [1]; limitation: some programs are single-threaded and cannot benefit from multiple cores [1].
Q8What is the role of the MDR and how does it differ from the MAR?[2]
✅ Mark scheme
Mark scheme
MDR holds the actual data read from or written to memory [1]; MAR holds the memory address to be accessed, not the data itself [1].
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Mini Test — Internal Hardware
10 questions · 10 minutes
⏱ 10:00
Section A — Multiple Choice [5 marks]
Q1Which register holds the address of the next instruction to be fetched?
Q2During the Fetch stage, after the instruction is fetched, the PC is:
Q3The address bus is:
Q4L1 cache compared to L3 cache is:
Q5The width of a 32-bit address bus limits RAM to a maximum of:
Section B — Short Answer [5 marks]
Q6State two operations performed by the ALU.
Mark schemeAny two from: addition, subtraction, multiplication, division (arithmetic) [1]; AND, OR, NOT, comparisons (logical) [1].
Q7What is the role of the Control Unit?
Mark schemeFetches and decodes instructions [1]; controls and coordinates all CPU components by generating control signals [1].
Q8What does MDR stand for and what does it hold?
Mark schemeMemory Data Register [1]; holds the data read from or to be written to memory [1].
Q9State one way increasing clock speed improves CPU performance and one disadvantage.
Mark schemeMore FDE cycles per second → instructions processed faster [1]; disadvantage: increased heat generation and power consumption [1].
Q10During the Fetch stage, describe what happens to the MAR.
Mark schemeThe address from the PC is copied into the MAR so the correct memory location can be accessed [1].