CISC vs RISC Architecture

Two major CPU design philosophies:

Pipelining

Pipelining is a technique where the CPU begins the next instruction's Fetch stage before the current instruction has finished its Execute stage. Like an assembly line — multiple instructions are in different stages simultaneously.

A simple 3-stage pipeline (Fetch, Decode, Execute) can process 3 instructions overlapping:

• Clock 1: Instruction 1 — Fetch
• Clock 2: Instruction 1 — Decode | Instruction 2 — Fetch
• Clock 3: Instruction 1 — Execute | Instruction 2 — Decode | Instruction 3 — Fetch
• Clock 4: Instruction 1 complete | Instruction 2 — Execute | Instruction 3 — Decode | Instruction 4 — Fetch

This increases throughput (instructions completed per second) without increasing clock speed.

Pipeline Hazards

• Data hazard: instruction needs result of a previous instruction not yet complete
• Control hazard (branch hazard): a branch instruction means it's unknown which instruction comes next
• Structural hazard: two instructions need the same hardware resource simultaneously

Interrupt Handling

An interrupt is a signal from hardware or software that the CPU needs to stop its current task and deal with something else. At the end of each FDE cycle, the CPU checks for interrupts.

• If an interrupt is found, the current PC and registers are pushed to a stack (saved)
• The CPU runs an Interrupt Service Routine (ISR) — the code that handles the interrupt
• When ISR completes, original register values are restored from the stack and the CPU continues

Virtual Memory

When RAM is full, the OS uses part of the hard disk as virtual memory. Pages of RAM are swapped to disk when needed. The process is called paging. Virtual memory allows programs larger than physical RAM to run, but is much slower due to disk access.