1.3.1 CPU Architecture — Cambridge 9618

The Central Processing Unit (CPU)

The CPU (Central Processing Unit) is the main component of a computer that executes program instructions. It consists of several key components connected by internal buses.

Arithmetic and Logic Unit (ALU)

The ALU performs all arithmetic operations (add, subtract, multiply, divide) and logical operations (AND, OR, NOT, XOR comparisons). It is the computational core of the CPU.

Arithmetic operations: addition, subtraction, multiplication, division
Logical/Boolean operations: AND, OR, NOT, XOR
Comparison operations: equal to, greater than, less than (used in conditional jumps)
Shift operations: left shift, right shift (used for multiplication/division by powers of 2)

Control Unit (CU)

The Control Unit directs and coordinates all CPU operations. It does NOT process data itself — it controls the flow of data and instructions throughout the CPU and to other components.

Fetches instructions from main memory
Decodes instructions to determine what operation is required
Sends control signals to the ALU, registers, and memory
Controls timing and sequencing of all CPU operations

Registers

Registers are small, ultra-fast storage locations within the CPU. Cambridge 9618 requires knowledge of these specific registers:

Register	Name	Purpose
PC	Program Counter	Holds the memory address of the next instruction to be fetched. Automatically incremented after each fetch.
MAR	Memory Address Register	Holds the memory address to be accessed (read from or written to). Connected to the address bus.
MDR	Memory Data Register	Temporarily holds data that has just been read from or is about to be written to memory. Connected to the data bus.
CIR	Current Instruction Register	Holds the instruction currently being decoded and executed by the Control Unit.
ACC	Accumulator	General-purpose register used by the ALU to hold intermediate results of calculations. Most ALU operations use the ACC.
IX	Index Register	Holds an index value used in indexed addressing mode — the effective address = base address + IX.

System Buses

Buses are groups of wires carrying data between CPU components and memory/I-O devices. There are three types:

ALU

Arithmetic & Logic
Unit

Control Unit

PC · MAR · MDR
CIR · ACC · IX

Registers

PC · MAR · MDR · CIR · ACC · IX · General Purpose

Address busUnidirectional
Memory addresses

Data busBidirectional
Data & instructions

Control busBidirectional
Control signals

Bus	Direction	Carries
Address bus	Unidirectional (CPU → memory/I/O)	Memory addresses; width = number of addressable locations (e.g. 32-bit address bus → 2³² locations)
Data bus	Bidirectional (both directions)	Data and instructions between CPU, memory, and I/O devices; width = word size (bits transferred per transfer)
Control bus	Bidirectional (various signals)	Control signals: read/write, clock, interrupt, bus request, etc.

Performance Factors

Clock speed (GHz) — number of clock cycles per second; higher = faster instruction execution
Word size — bits processed per cycle; wider word → more data processed per operation
Number of cores — multiple cores allow parallel processing of independent threads
Cache size — larger cache reduces time waiting for data from slower RAM
Bus width — wider data bus transfers more data per cycle; wider address bus addresses more memory

Exam tip: Cambridge 9618 requires you to know ALL six registers by name and purpose. The most commonly tested are PC (next instruction address), MAR (address being accessed), MDR (data to/from memory), and CIR (instruction being decoded). Remember: wider address bus = more addressable locations; wider data bus = more data per transfer; control bus carries READ, WRITE, CLOCK, INTERRUPT signals.

⚠️ Common Mistakes

Saying the PC holds the current instruction — the PC holds the address of the NEXT instruction; the CIR holds the current instruction being decoded
Saying the MDR holds an address — the MDR holds DATA; the MAR holds the ADDRESS
Saying the address bus is bidirectional — the address bus is UNIDIRECTIONAL (CPU to memory)
Confusing ALU and CU — the ALU processes data; the CU controls/coordinates operations but does not process data

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Worksheet — 1.3.1 CPU Architecture

8 questions · instantly marked · Cambridge 9618 standard

Q1State the purpose of the ALU and the Control Unit, explaining the difference between them.[4]

✅ Mark scheme

Mark scheme

The ALU performs arithmetic operations (add, subtract) and logical/Boolean operations (AND, OR, NOT) — it is the computational component of the CPU [2]; the Control Unit directs and coordinates all CPU operations — it fetches and decodes instructions and sends control signals to other components but does not perform calculations itself [2].

Q2State the purpose of the Program Counter (PC) and the Current Instruction Register (CIR), explaining the difference.[4]

✅ Mark scheme

Mark scheme

The PC holds the memory address of the next instruction to be fetched — it is automatically incremented after each fetch [2]; the CIR holds the instruction currently being decoded and executed by the Control Unit [2].

Q3Explain the difference between the MAR and the MDR.[4]

✅ Mark scheme

Mark scheme

The MAR (Memory Address Register) holds the address in memory to be accessed — it is connected to the address bus [2]; the MDR (Memory Data Register) holds the data that has been read from memory or is about to be written to memory — it is connected to the data bus [2].

Q4Describe the three system buses and state whether each is unidirectional or bidirectional.[6]

✅ Mark scheme

Mark scheme

Address bus: carries memory addresses from CPU to memory/I-O; unidirectional [2]; Data bus: carries data and instructions between CPU, memory, and I-O devices; bidirectional [2]; Control bus: carries control signals (read, write, clock, interrupt) between CPU and other components; bidirectional [2].

Q5Explain how the width of the address bus affects the amount of memory a CPU can access.[3]

✅ Mark scheme

Mark scheme

The address bus carries memory addresses; each wire represents one bit [1]; a wider address bus can carry larger addresses — a 32-bit address bus can address 2³² (approximately 4 billion) memory locations [1]; increasing the address bus width allows the CPU to address more memory [1].

Q6State the purpose of the Index Register (IX) in the Cambridge 9618 processor model.[2]

✅ Mark scheme

Mark scheme

The IX (Index Register) holds an index value used in indexed addressing mode [1]; the effective address = base address + IX — allowing iteration through arrays or data structures [1].

Q7State four factors that affect CPU performance.[4]

✅ Mark scheme

Mark scheme

1 mark each for any four: clock speed (GHz) — more cycles per second; word size — more data processed per cycle; number of cores — parallel processing; cache size — reduces RAM access latency; bus width — more data/larger addresses per transfer.

Q8A CPU has a 32-bit address bus and a 64-bit data bus. State what each of these widths tells you about the CPU's capability.[4]

✅ Mark scheme

Mark scheme

32-bit address bus: the CPU can address 2³² = approximately 4 billion (4 GB) unique memory locations [2]; 64-bit data bus: the CPU can transfer 64 bits (8 bytes) of data per memory access/transfer — a wider data bus means more data transferred per cycle [2].

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Term	Definition

The Central Processing Unit (CPU)

Arithmetic and Logic Unit (ALU)

Control Unit (CU)

Registers

System Buses

Performance Factors

Worksheet — 1.3.1 CPU Architecture

Mini Test — 1.3.1 CPU Architecture