Cambridge 9618 · International A Level Computer Science · ~14 min read
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The Fetch-Decode-Execute (FDE) Cycle
The FDE Cycle is the fundamental process by which a CPU processes instructions. It repeats continuously as long as the computer is running. Each cycle consists of three stages: Fetch, Decode, Execute.
1. Fetch
Get instruction from memory
→
2. Decode
Interpret instruction
→
3. Execute
Carry out instruction
→
Repeat
Next instruction
Fetch Stage — Detailed Steps
Step
What happens
Registers involved
1
The address in the PC is copied to the MAR
PC → MAR
2
The PC is incremented by 1 (ready for the next instruction)
PC + 1 → PC
3
The instruction at the address in MAR is fetched from memory and placed in the MDR (via the data bus)
Memory[MAR] → MDR
4
The instruction in the MDR is copied to the CIR
MDR → CIR
Decode Stage
The Control Unit decodes the instruction in the CIR by splitting it into its component parts:
Opcode — the operation code that specifies what operation to perform (e.g. ADD, LOAD, STORE, JUMP)
Operand — the data or memory address the operation acts upon
The Control Unit determines which signals need to be sent to the ALU, registers, and memory to carry out the instruction.
Execute Stage
The instruction is carried out. The execute stage varies depending on the opcode:
Arithmetic/logical: ALU performs the operation; result placed in ACC
Memory read: Address placed in MAR → data fetched to MDR → moved to register
Memory write: Data placed in MDR → address in MAR → data written to memory
Jump (conditional/unconditional): PC is set to the jump address if the condition is met
I/O operations: Data is read from/written to I/O device
Interrupts
An interrupt is a signal sent to the CPU by hardware or software requesting immediate attention. After the execute stage, the CPU checks for pending interrupts before fetching the next instruction.
If an interrupt is pending and its priority is sufficient, the CPU saves its current state (registers + PC) to a stack
The CPU then executes the Interrupt Service Routine (ISR) — code that handles the interrupt
After the ISR completes, the CPU restores its saved state from the stack and resumes where it left off
Examples of interrupts: I/O completion, hardware fault, timer, software exception (division by zero).
Improving CPU Performance
Several techniques are used to speed up instruction processing:
Pipelining: While one instruction is in the Execute stage, the next is being Decoded, and the one after is being Fetched — multiple instructions in different stages simultaneously. Increases throughput without increasing clock speed.
Superscalar processing: Multiple pipelines execute instructions in parallel
Out-of-order execution: Instructions are executed in a different order to the program to avoid waiting for dependencies
Branch prediction: The CPU speculatively executes instructions after a conditional branch before the condition is evaluated
Exam tip: Cambridge questions often ask you to describe the FDE cycle in register-level detail. Always name both the source and destination registers at each step. Remember: PC is copied to MAR first (so PC can be incremented safely); the PC increments during the FETCH stage (not decode or execute). Interrupts are checked between execute and the next fetch.
⚠️ Common Mistakes
Saying the PC increments during the execute stage — the PC increments during the FETCH stage (simultaneously with or just after the address is copied to MAR)
Saying the instruction is decoded in the MAR or MDR — the instruction is decoded when it is in the CIR by the Control Unit
Confusing opcode and operand — opcode specifies the operation (ADD, LOAD); operand is the data/address it acts on
Saying pipelining increases clock speed — pipelining increases throughput by overlapping stages; it does not increase the clock speed itself
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Worksheet — 1.3.2 FDE Cycle
8 questions · instantly marked · Cambridge 9618 standard
Q1Describe the Fetch stage of the FDE cycle in register-level detail, naming all registers used.[4]
✅ Mark scheme
Mark scheme
Address in PC is copied to MAR [1]; PC is incremented by 1 (so it points to the next instruction) [1]; the instruction at the address held in MAR is fetched from memory via the data bus into the MDR [1]; the instruction is copied from the MDR to the CIR [1].
Q2Explain what happens during the Decode stage of the FDE cycle.[3]
✅ Mark scheme
Mark scheme
The Control Unit decodes the instruction held in the CIR [1]; it splits the instruction into opcode (the operation to be performed) and operand (the data or address to act upon) [1]; the CU determines which control signals need to be sent to execute the instruction [1].
Q3Describe what an interrupt is and explain how the CPU handles an interrupt at the end of the execute stage.[5]
✅ Mark scheme
Mark scheme
An interrupt is a signal to the CPU requesting immediate attention from hardware or software [1]; after execute, the CPU checks for pending interrupts [1]; if a high-priority interrupt is present, the CPU saves its current state (register values and PC) to a stack [1]; the CPU then executes the Interrupt Service Routine (ISR) to handle the interrupt [1]; once the ISR completes, the saved state is restored from the stack and normal processing resumes [1].
Q4Explain what pipelining is and how it improves CPU performance.[4]
✅ Mark scheme
Mark scheme
Pipelining overlaps the stages of the FDE cycle for multiple instructions simultaneously [1]; while one instruction is being executed, the next is being decoded, and the one after is being fetched [1]; this increases throughput — more instructions are completed per unit time [1]; it does not increase the clock speed but makes better use of each clock cycle [1].
Q5Explain the difference between an opcode and an operand.[2]
✅ Mark scheme
Mark scheme
The opcode specifies the operation to be performed (e.g. ADD, LOAD, STORE, JUMP) [1]; the operand is the data or memory address the operation acts upon [1].
Q6During which stage of the FDE cycle is the Program Counter incremented? Explain why this is important.[3]
✅ Mark scheme
Mark scheme
The PC is incremented during the Fetch stage [1] — after the address is copied to MAR so the original value is preserved [1]; incrementing the PC ensures that after the current instruction is executed, the CPU will fetch the next instruction in sequence [1].
Q7Describe the execute stage for an instruction that reads a value from memory.[3]
✅ Mark scheme
Mark scheme
The memory address is placed in the MAR [1]; the value at that memory address is fetched via the data bus and placed in the MDR [1]; the value is copied from the MDR to the destination register (e.g. ACC) [1].
Q8Explain why pipelining can sometimes fail to improve performance.[3]
✅ Mark scheme
Mark scheme
A conditional branch (jump) causes a pipeline hazard — if the branch is taken, instructions already in the pipeline from the wrong path must be discarded (pipeline flush/stall) [1]; this wastes cycles and reduces efficiency [1]; branch prediction is used to speculatively continue filling the pipeline — but if the prediction is wrong, a flush still occurs [1].
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Mini Test — 1.3.2 FDE Cycle
10 questions · 10 marks · 10 minutes
⏱ 10:00
10 marks
Section A — Multiple Choice [5 marks]
Q1What is the FIRST step of the Fetch stage?
Q2During which stage is the instruction decoded?
Q3An interrupt is handled after which stage?
Q4Pipelining improves CPU performance by:
Q5When handling an interrupt, the CPU saves its current state to:
Section B — Short Answer [5 marks]
Q6State the four steps of the Fetch stage in order.
Mark schemePC → MAR; PC incremented; memory[MAR] → MDR; MDR → CIR [1 mark for all four in correct order].
Q7State what opcode and operand mean in the context of a machine instruction.
Mark schemeOpcode: specifies the operation to perform (e.g. ADD, LOAD); operand: the data or address the operation acts on [1 mark].
Q8After an ISR completes, what does the CPU do?
Mark schemeThe CPU restores its saved state (register values and PC) from the stack and resumes normal processing from where it left off [1 mark].
Q9Give one reason why pipelining may fail to improve performance.
Mark schemeA branch instruction causes a pipeline hazard/stall — if the branch is taken, instructions already partially processed in the pipeline from the wrong path are discarded (flushed), wasting cycles [1 mark].
Q10State why the PC is incremented during the Fetch stage rather than the Execute stage.
Mark schemeThe PC is incremented during Fetch (after copying to MAR) so that by the time the current instruction is executed, the PC already points to the next instruction in sequence [1 mark].