📁 Component 1 · 1.1 Contemporary Processors
1.1.1a The CPU, ALU, Control Unit and Registers
OCR H446 · A Level Computer Science · ~14 min read
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The Stored Program Concept and Von Neumann Architecture

The stored program concept, developed by John von Neumann in the 1940s, states that both program instructions and data are stored together in the same memory (RAM) in binary form. The CPU fetches each instruction from memory, decodes it, and executes it sequentially. This is the foundation of virtually all modern computers.

The key insight of Von Neumann architecture is that because instructions are stored as binary data, the same memory can hold both a program and the data it operates on. This allows programs to be loaded and changed without altering the hardware — unlike earlier machines where programs were hardwired.

Components of the CPU

Control Unit (CU)

The Control Unit is the component that coordinates all CPU operations. It does not perform calculations itself, but instead:

  • Fetches instructions from memory
  • Decodes (interprets) each instruction to determine what must be done
  • Sends control signals to other components to carry out the instruction
  • Controls the timing and sequencing of all operations via the control bus

Arithmetic Logic Unit (ALU)

The ALU performs all computational operations on data. At A Level, you need to know the ALU handles three types of operation:

  • Arithmetic operations: addition, subtraction, multiplication, division
  • Logical operations: AND, OR, NOT, XOR (bitwise)
  • Shift operations: logical left/right shift and arithmetic shift of binary values

Results of ALU operations are stored temporarily in the Accumulator register.

Registers

Registers are extremely fast, small storage locations inside the CPU. They hold values that are currently being processed. Accessing a register is far faster than accessing main memory (RAM), which is why registers are used for active data during processing.

RegisterFull NamePurpose
PCProgram CounterHolds the memory address of the next instruction to be fetched. Increments after each fetch.
MARMemory Address RegisterHolds the address in memory that is being accessed (read from or written to).
MDRMemory Data RegisterHolds the data being transferred to or from the memory address held in the MAR.
CIRCurrent Instruction RegisterHolds the instruction currently being decoded and executed.
ACCAccumulatorHolds the result of the most recent ALU operation.
SRStatus RegisterHolds individual flag bits that record the outcome of the last operation (carry, zero, negative, overflow).
GPRGeneral Purpose RegistersHold intermediate values and operands. Having multiple GPRs reduces memory accesses and increases speed.

The Status Register (A Level specific)

The status register contains individual bits called flags that record the outcome of the last arithmetic or logical operation:

  • Carry flag (C): set if the result produced a carry out of the most significant bit
  • Zero flag (Z): set if the result is zero
  • Negative flag (N): set if the result is negative (MSB = 1)
  • Overflow flag (V): set if signed arithmetic produced an overflow

The status register is used by conditional branch instructions — the CPU checks flags to decide whether to jump to a different part of the program.

General Purpose Registers (A Level specific)

Modern processors include multiple general purpose registers (e.g., R0–R15 in ARM). These hold operands and intermediate results during computation, avoiding the need to constantly read from and write to slower RAM. More general purpose registers generally mean fewer memory accesses and faster execution.

The Three Buses

Buses are sets of parallel wires that transfer data between CPU components and main memory:

  • Address bus: carries memory addresses from CPU to RAM (one-directional, CPU → memory)
  • Data bus: carries data or instructions between CPU and memory (bidirectional)
  • Control bus: carries control signals (e.g., read/write signals) from the Control Unit (bidirectional)

The width of the address bus determines the maximum addressable memory (2n locations for an n-bit bus). The width of the data bus determines how many bits are transferred per clock cycle.

Exam tip: At A Level, you must know the status register and its flags (carry, zero, negative, overflow) — this is not required at GCSE. The flags are tested by conditional branch instructions.
Exam tip: The distinction between MAR (holds an address) and MDR (holds data) is regularly tested. The MAR is connected to the address bus; the MDR is connected to the data bus.
⚠ Common Mistakes
  • Saying the CU performs calculations — it does not. The ALU performs calculations; the CU coordinates.
  • Confusing MAR (address) with MDR (data) — remember: R in MAR = Address, R in MDR = Data.
  • Forgetting that the PC holds the address of the next instruction, not the current one.
  • Omitting the status register or general purpose registers from A Level answers about CPU registers.
  • Stating the address bus is bidirectional — it is unidirectional (CPU to memory only).
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Exam-style Worksheet — 1.1.1a CPU, ALU, Control Unit and Registers

8 OCR H446-style questions · 20 marks total · instantly marked with personalised feedback

Q1What is meant by the stored program concept?[2 marks]
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Both program instructions and data are stored together in main memory (RAM) [1] in binary form, and the CPU fetches and executes instructions sequentially from memory [1].
Q2Describe the role of the Control Unit (CU) within the CPU.[2 marks]
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The CU coordinates and controls all CPU operations [1]; it fetches and decodes instructions, and sends control signals to other components to direct their activity (does not perform calculations itself) [1].
Q3State three types of operation that the ALU can perform.[3 marks]
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Any three from: arithmetic operations (e.g. addition, subtraction) [1]; logical operations (e.g. AND, OR, NOT, XOR) [1]; shift operations (logical/arithmetic left or right shift) [1]; comparison operations (e.g. greater than, equal to) [1].
Q4Explain the purpose of the status register and name two flags it contains.[3 marks]
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The status register holds individual flag bits that record the outcome/result of the most recent arithmetic or logical operation [1], and these flags are used by conditional branch instructions to control program flow [1]. Any two flags: carry flag (result produced a carry) / zero flag (result is zero) / negative flag (result is negative) / overflow flag (signed overflow occurred) [1].
Q5Distinguish between the MAR and the MDR, stating which bus each is connected to.[2 marks]
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The MAR (Memory Address Register) holds the memory address being accessed and is connected to the address bus [1]; the MDR (Memory Data Register) holds the data being read from or written to that address and is connected to the data bus [1].
Q6Explain one advantage of having multiple general purpose registers in a processor.[2 marks]
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Multiple general purpose registers allow intermediate results and operands to be held inside the CPU [1], reducing the number of slow accesses to main memory and therefore increasing the speed of execution [1].
Q7A processor has a 32-bit address bus. Calculate the maximum amount of memory it can directly address. Show your working.[2 marks]
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Maximum addressable locations = 2²² = 4,294,967,296 [1]; this equals 4 GB (gigabytes) [1]. Accept 2²² bytes / 4 × 2³⁰ bytes.
Q8A student claims that Von Neumann architecture is a disadvantage because “the CPU has to share a single memory bus for both fetching instructions and accessing data.” Explain what this limitation is called and suggest one way it can be overcome.[4 marks]
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The limitation is known as the Von Neumann bottleneck [1]; because instructions and data share the same bus, the CPU must alternate between fetching instructions and accessing data, creating a bottleneck that limits throughput [1]. One solution: cache memory between CPU and RAM so frequently accessed data/instructions are stored closer to the CPU [1], reducing the number of accesses to slower main memory and alleviating the bottleneck [1]. Alternatively: Harvard architecture (separate instruction and data buses/memories) — award marks as appropriate.
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Mini Test — 1.1.1a CPU, ALU, CU and Registers

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1.1.1 Structure and Function of the Processor Next: 1.1.1b System Buses and Memory →
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