1.1.1b The System Buses and Memory — OCR H446

The System Buses

A bus is a set of parallel wires (or traces on a circuit board) that transfer binary data between components. The three main buses connect the CPU to main memory and I/O controllers:

Bus	Direction	What it carries	Connected to
Address bus	Unidirectional (CPU → memory)	Memory addresses	MAR on CPU side
Data bus	Bidirectional	Data and instructions	MDR on CPU side
Control bus	Bidirectional	Control signals (read, write, clock, interrupt, bus request)	Control Unit on CPU side

Bus Width and Performance

Bus width is the number of parallel lines (bits) in the bus. Wider buses transfer more data per clock cycle:

Address bus width determines the maximum addressable memory: an n-bit address bus can access 2ⁿ locations. A 32-bit address bus gives 2³² = 4 GB maximum; a 64-bit bus gives 2⁶⁴ locations (vastly more than any current system needs).
Data bus width determines how many bits are transferred per transaction. A 64-bit data bus transfers 8 bytes at once, doubling the throughput of a 32-bit bus.

Bus speed (in MHz or GHz) also affects throughput. Total bandwidth = bus width × bus speed.

Memory Hierarchy

There is a fundamental trade-off in memory design: speed vs. capacity vs. cost. Faster memory is more expensive per bit and typically smaller. The memory hierarchy organises storage by this trade-off:

Level	Type	Speed	Capacity	Cost/bit	Volatile?
1 — Registers	Inside CPU (flip-flops)	~1 cycle	Bytes	Highest	Yes
2 — L1 Cache	SRAM, on-chip	2–4 cycles	32–256 KB	Very high	Yes
3 — L2 Cache	SRAM, on-chip	6–20 cycles	256 KB–4 MB	High	Yes
4 — L3 Cache	SRAM, shared	20–60 cycles	4–64 MB	Moderate-high	Yes
5 — RAM	DRAM	60–100 cycles	GBs	Low	Yes
6 — Secondary	SSD / HDD	Thousands of cycles	TBs	Very low	No

SRAM vs DRAM

SRAM (Static RAM) uses flip-flops (6 transistors per bit) to store each bit. It retains data as long as power is supplied and does not need refreshing. It is faster but more expensive and uses more silicon area, so it is used for cache.

DRAM (Dynamic RAM) uses a capacitor and single transistor per bit. Capacitors leak charge, so DRAM must be refreshed thousands of times per second. This makes it slower than SRAM but much cheaper and denser, making it suitable for main memory (RAM).

Cache Memory

Cache is a small, fast bank of SRAM placed between the CPU and main memory. Its purpose is to reduce the effective access time by storing copies of frequently and recently accessed data and instructions.

Locality of reference explains why cache works:

Temporal locality: recently accessed data is likely to be accessed again soon (e.g. loop variables)
Spatial locality: data near recently accessed locations is likely to be needed soon (e.g. sequential array elements)

Cache hit: the CPU finds the required data in cache — very fast. Cache miss: data is not in cache, so the CPU must fetch it from RAM — much slower. The hit rate is the proportion of accesses satisfied from cache. A higher hit rate means better performance.

Modern processors use multi-level caches (L1, L2, L3). L1 is smallest and fastest (per core); L3 is largest and shared between cores.

Memory-Mapped I/O

In memory-mapped I/O, I/O device registers are assigned addresses in the same address space as RAM. The CPU reads from and writes to device registers using the same instructions as for memory access, via the address and data buses. This simplifies the instruction set because no separate I/O instructions are needed.

Exam tip: The address bus is unidirectional — this is frequently tested. The data bus is bidirectional (CPU reads from AND writes to memory). The control bus is also bidirectional (sends signals AND receives interrupt signals).

Exam tip: Know the difference between SRAM (fast, no refresh, used in cache) and DRAM (slow, needs refresh, used in RAM). SRAM uses flip-flops; DRAM uses capacitors.

⚠ Common Mistakes

Saying a wider address bus increases transfer speed — it increases addressable memory, not speed.
Confusing SRAM and DRAM — SRAM is for cache; DRAM is for main RAM.
Forgetting that DRAM needs periodic refreshing — this is what makes it slower.
Saying L1 cache is shared between cores — typically each core has its own L1 (and L2); L3 is shared.

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Worksheet — 1.1.1b System Buses and Memory

8 questions · 20 marks · instantly marked

Q1State the direction of data flow on the address bus and explain why it is designed this way.[2 marks]

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The address bus is unidirectional, carrying addresses from the CPU to memory (and I/O) only [1]; this is because only the CPU generates memory addresses — memory never needs to send addresses back to the CPU [1].

Q2A processor has a 32-bit address bus and a 64-bit data bus running at 1600 MHz. Calculate the maximum addressable memory in gigabytes.[2 marks]

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Mark scheme

2²² = 4,294,967,296 addresses [1]; since each address accesses 1 byte, maximum RAM = 4 GB [1]. (Note: the data bus width and speed do not affect the amount of addressable memory.)

Q3Explain the difference between SRAM and DRAM in terms of structure and the need for refreshing.[4 marks]

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SRAM uses flip-flops (typically 6 transistors per bit) to store data [1] and retains data without refreshing as long as power is supplied [1]; DRAM uses a capacitor (and 1 transistor) per bit [1], but the capacitor leaks charge so must be periodically refreshed (thousands of times per second) to prevent data loss [1].

Q4Why is SRAM used for cache memory rather than DRAM?[2 marks]

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Mark scheme

SRAM is faster than DRAM because it does not need refreshing [1]; cache must supply data to the CPU with minimal delay, and SRAM can match CPU clock speeds (DRAM cannot) [1]. Accept: SRAM does not need a refresh cycle so has lower latency.

Q5Explain the concepts of temporal and spatial locality of reference and how they justify the use of cache memory.[4 marks]

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Temporal locality: recently accessed data/instructions are likely to be needed again soon (e.g. loop variables) [1]; spatial locality: data near recently accessed addresses is likely to be needed soon (e.g. sequential array elements) [1]; because of temporal locality, keeping recently used data in fast cache means future accesses are likely to be cache hits [1]; because of spatial locality, loading blocks of memory (cache lines) into cache in advance is likely to hold data that will soon be needed [1].

Q6Define cache hit rate and explain how it affects overall system performance.[2 marks]

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Hit rate is the proportion (or percentage) of memory accesses that are satisfied from the cache rather than from main memory [1]; a higher hit rate reduces the average memory access time because more accesses are served at cache speed rather than slower RAM speed, improving overall performance [1].

Q7Describe how memory-mapped I/O works and give one advantage of this approach over having separate I/O instructions.[2 marks]

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Mark scheme

In memory-mapped I/O, device registers are assigned addresses within the same address space as main memory [1] so the CPU accesses devices using the same read/write instructions as for memory, without needing separate I/O instructions, simplifying the instruction set [1].

Q8A student says “increasing the width of the data bus from 32 bits to 64 bits will double the maximum addressable memory.” Evaluate this claim.[2 marks]

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Mark scheme

The claim is incorrect [1]; maximum addressable memory is determined by the address bus width (2ⁿ locations for n address bits), not the data bus width. Widening the data bus increases the amount of data transferred per clock cycle (bandwidth) but does not change the number of addressable locations [1].

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The System Buses

Bus Width and Performance

Memory Hierarchy

SRAM vs DRAM

Cache Memory

Memory-Mapped I/O

Worksheet — 1.1.1b System Buses and Memory

Mini Test — 1.1.1b System Buses and Memory