OCR H446 · A Level Computer Science · ~13 min read
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CISC: Complex Instruction Set Computer
A CISC architecture has a large number of instructions, many of which are complex and can perform multiple operations (such as memory access and arithmetic) in a single instruction.
Key characteristics of CISC:
Large instruction set: hundreds of different instructions, including complex ones (e.g. an instruction that multiplies two numbers from memory and writes the result back to memory).
Variable instruction length: instructions can be different lengths (e.g. 1–8 bytes in x86), making pipelining more complex.
Memory-to-memory operations: instructions can directly read from and write to memory, without needing separate LOAD/STORE instructions.
Fewer general purpose registers: since instructions can access memory directly, fewer registers are needed.
Complex decoder: the Control Unit requires extensive logic (microcode) to decode complex instructions.
Ease of programming (especially assembly): complex instructions reduce the number of lines of assembly code a programmer must write.
Examples: Intel x86, AMD x86-64 (used in most desktop/laptop computers).
RISC: Reduced Instruction Set Computer
A RISC architecture uses a smaller set of simple, uniform instructions. Each instruction performs exactly one operation, and instructions have a fixed length.
Key characteristics of RISC:
Small instruction set: only simple, commonly-used instructions are implemented in hardware.
Fixed instruction length: every instruction is the same number of bits (e.g. 32 bits for ARM), making pipelining much simpler and more efficient.
Load-store architecture: only LOAD and STORE instructions access memory; all other instructions (arithmetic, logical) operate exclusively on registers.
Many general purpose registers: since arithmetic instructions cannot access memory directly, data must be in registers, requiring many registers.
Simple decoder: uniform, simple instructions can be decoded in a single clock cycle (hardwired control unit, no microcode).
More efficient pipelining: fixed-length instructions are much easier to pipeline, often achieving higher throughput per clock cycle.
Compiler dependency: the compiler must generate more instructions to accomplish the same task (since each instruction does less).
Examples: ARM (used in smartphones, tablets, Apple M-series chips), MIPS, RISC-V.
CISC vs RISC Comparison
Feature
CISC
RISC
Instruction set size
Large (many complex instructions)
Small (few simple instructions)
Instruction length
Variable
Fixed
Memory access
Any instruction can access memory
Only LOAD/STORE access memory
Number of GPRs
Fewer
More
Instruction execution time
Variable (some instructions take many cycles)
Typically 1 cycle per instruction
Pipelining efficiency
Harder (variable-length instructions)
Easier (fixed-length instructions)
Control unit
Complex (uses microcode)
Simple (hardwired)
Code density
Higher (fewer instructions needed)
Lower (more instructions for same task)
Power consumption
Higher
Lower
Typical use
Desktop/server computers
Mobile devices, embedded systems, some servers
Modern Processors and Hybrid Approaches
Modern CISC processors (like Intel x86) actually translate CISC instructions into simpler internal micro-operations (μops) at the hardware level, effectively implementing a RISC core internally. This blurs the boundary between CISC and RISC. Modern ARM processors have also adopted some CISC-like extensions (e.g. NEON SIMD instructions) for multimedia performance.
Exam tip: The key distinguishing feature of RISC is the load-store architecture — only LOAD and STORE instructions access memory. All arithmetic and logical instructions work exclusively on registers. This is the most frequently tested RISC characteristic at A Level.
Exam tip: OCR exam questions often ask you to compare CISC and RISC for a specific purpose (e.g. smartphones, server workloads). Think: mobile needs low power and heat → RISC (ARM). High-performance desktop → CISC (x86) with complex multi-media instructions.
⚠ Common Mistakes
Saying RISC has no instructions — it has a reduced set of simple instructions, not no instructions.
Saying RISC is always faster than CISC — modern CISC processors are competitive because they internally use RISC-like micro-operations.
Confusing which has more registers — RISC has more registers; CISC has fewer (since CISC instructions can access memory directly).
Saying CISC instructions execute in 1 cycle — CISC instructions can take multiple cycles; RISC instructions aim for 1 cycle each.
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Worksheet — 1.1.2a CISC and RISC Architectures
8 questions · 20 marks · instantly marked
Q1State two characteristics of a CISC processor that distinguish it from a RISC processor.[2 marks]
✓ Mark scheme
Any two from: large instruction set with complex instructions [1]; variable instruction length [1]; instructions can directly access memory (not load-store) [1]; fewer general purpose registers [1]; uses microcode for decoding [1].
Q2Explain what is meant by a 'load-store architecture' and state which type of processor uses it.[3 marks]
✓ Mark scheme
A load-store architecture is one in which only LOAD and STORE instructions can access main memory [1]; all other instructions (arithmetic, logical, comparison) operate exclusively on data held in registers [1]; RISC processors use this architecture [1].
Q3Explain why RISC processors are typically better suited to pipelining than CISC processors.[3 marks]
✓ Mark scheme
RISC instructions are fixed length [1], making it straightforward to identify the boundaries between instructions and begin fetching the next instruction before the current one has finished [1]; CISC instructions are variable length, so the CPU must determine each instruction's length before it can fetch the next, complicating pipelining and requiring stalls [1].
Q4Why do RISC processors typically have more general purpose registers than CISC processors?[2 marks]
✓ Mark scheme
RISC uses a load-store architecture, so all arithmetic and logical operations must use data already in registers [1]; more registers are therefore needed to hold operands and intermediate results without repeatedly loading from and storing to slower memory [1].
Q5A smartphone manufacturer is choosing between ARM (RISC) and Intel x86 (CISC) for their new device. Give two reasons why ARM would be more suitable.[2 marks]
✓ Mark scheme
Any two from: ARM (RISC) has lower power consumption, extending battery life [1]; ARM generates less heat, reducing the need for active cooling (no fan needed in phones) [1]; ARM is suitable for embedded/mobile systems where power efficiency is critical [1]; smaller, simpler hardware [1].
Q6Describe how modern CISC processors (such as Intel x86) have adopted elements of RISC design.[2 marks]
✓ Mark scheme
Modern CISC processors translate incoming CISC instructions into simpler internal micro-operations (μops) [1]; these micro-operations are RISC-like (fixed length, simple operations) and are executed by an internal RISC-style core, allowing pipelining and out-of-order execution to be applied effectively [1].
Q7Explain why RISC programs may require more memory to store than equivalent CISC programs.[2 marks]
✓ Mark scheme
RISC instructions each perform only one simple operation [1]; therefore more instructions are needed to perform the same task as a single complex CISC instruction, resulting in longer programs (lower code density) that occupy more memory [1].
Q8A CISC instruction performs: “MULTIPLY the value at memory address 2000 by the value at memory address 2004 and write the result to address 2008.” Write the equivalent sequence of RISC instructions (using LOAD Rn, addr / MUL Rd, Rs1, Rs2 / STORE Rd, addr format). How many instructions does this require?[4 marks]
✓ Mark scheme
Four instructions are required [1]: LOAD R1, 2000 — load first operand from memory into register R1 [1]; LOAD R2, 2004 — load second operand from memory into register R2 [1]; MUL R3, R1, R2 — multiply R1 and R2, store result in R3 (works only on registers) [1]; STORE R3, 2008 — store result to memory address 2008 [1]. (Award 1 mark for the four-step structure, 1 mark for each correct LOAD, 1 for MUL, 1 for STORE — max 4.)
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Mini Test — 1.1.2a CISC and RISC
Timed exam conditions.
10 questions · 10 marks · 10 minutes
5 MCQ + 5 short answer
⏱10:00
10 marks
Section A — Multiple Choice
Q1Which architecture uses a load-store design where only LOAD and STORE instructions access memory?
Q2RISC processors have more general purpose registers than CISC because:
Q3Which characteristic of RISC makes pipelining more efficient than in CISC?
Q4The Intel x86 architecture is an example of:
Q5Why might a RISC program require more memory than an equivalent CISC program?
Section B — Short Answer
Q6State what type of instruction can access memory in a RISC load-store architecture.
Mark schemeOnly LOAD and STORE instructions can access memory. [1 mark]
Q7State the name of an example RISC processor architecture used in smartphones.
Mark schemeARM (also accept: MIPS, RISC-V). [1 mark]
Q8State one reason why CISC instructions have variable length.
Mark schemeDifferent instructions require different amounts of information (operands/addressing modes), so complex instructions need more bytes than simple ones. [1 mark]
Q9State one advantage of a CISC architecture over RISC for software developers writing assembly code.
Mark schemeFewer instructions are needed to write the same program (higher code density), making assembly programming simpler and programs shorter. [1 mark]
Q10Modern CISC processors translate CISC instructions into micro-operations internally. State the type of processor these micro-operations resemble.
Mark schemeThe micro-operations resemble RISC instructions (simple, fixed-length operations that work on registers). [1 mark]