1.1.1d CPU Performance and Pipelining — OCR H446

Factors Affecting CPU Performance

Several factors determine how fast a CPU can process instructions. OCR H446 requires you to know and evaluate these:

Factor	How it affects performance
Clock speed	Measured in GHz (billions of cycles per second). A higher clock speed means more FDE cycles per second and faster execution, assuming other factors are constant.
Number of cores	Each core has its own ALU, CU and registers. Multiple cores can execute different threads simultaneously (true parallelism), improving throughput for multi-threaded workloads.
Cache size	Larger cache can store more frequently used data close to the CPU, increasing hit rate and reducing average memory access time.
Word length	The width of the data bus and registers. A 64-bit processor can process 64-bit values in a single operation, handling more data per cycle than a 32-bit processor.
Pipelining	Overlapping execution of multiple instructions to maximise utilisation of CPU components (see below).

Pipelining

Pipelining is a technique that allows the CPU to work on multiple instructions simultaneously by overlapping the fetch, decode and execute stages. Without pipelining, each instruction must complete all three stages before the next one begins. With pipelining, as soon as one instruction moves from fetch to decode, the next instruction begins its fetch stage.

In a simple 3-stage pipeline:

While instruction 3 is being fetched, instruction 2 is being decoded and instruction 1 is being executed.
Instead of completing 1 instruction every 3 cycles, a steady-state pipeline completes 1 instruction per cycle.
A 3-stage pipeline can theoretically achieve a 3× speedup over a non-pipelined design.

Pipeline Hazards

Pipeline hazards are situations that disrupt the smooth flow of instructions through the pipeline, causing a stall (also called a bubble — idle pipeline stages).

Hazard type	Cause	Example / Mitigation
Structural hazard	Two stages need the same hardware resource at the same time (e.g. a single memory port needed for both fetch and data access).	Mitigated by having separate instruction cache and data cache (Harvard-style caches), or additional hardware units.
Data hazard	An instruction depends on the result of a previous instruction that hasn't yet completed its execute stage.	Mitigated by operand forwarding (bypassing — passing the result directly from ALU output to the next instruction's input), or by stalling (inserting NOPs).
Control hazard	A branch instruction changes the PC, but the pipeline has already begun fetching/decoding subsequent sequential instructions that may not be needed.	Mitigated by branch prediction: the CPU predicts whether a branch will be taken and prefetches accordingly. If wrong, the incorrectly fetched instructions are flushed (pipeline flush).

Branch Prediction

Branch prediction is a technique used to avoid control hazards. The CPU predicts whether a conditional branch will be taken and continues fetching instructions based on that prediction. If the prediction is correct, no stall occurs. If the prediction is wrong, the instructions fetched speculatively are flushed from the pipeline and the correct instructions are fetched, causing a penalty.

Modern processors use sophisticated dynamic branch predictors that track the history of branch outcomes to make more accurate predictions (often >95% accuracy).

Exam tip: Know all three types of pipeline hazard by name and be able to describe each. OCR exams frequently ask you to describe a hazard and explain how it can be mitigated.

Exam tip: In evaluation questions, note that increasing clock speed increases power consumption and heat. More cores don't improve single-threaded performance. Cache size has diminishing returns as it grows (larger cache = higher latency).

⚠ Common Mistakes

Saying pipelining makes individual instructions faster — it doesn't. It increases throughput (instructions per second) but each instruction still takes the same number of stages.
Confusing structural, data and control hazards — learn a clear example of each.
Saying more cores always means faster performance — only for workloads with multiple independent threads.
Forgetting that a branch misprediction causes a pipeline flush (wasted cycles), not just a stall.

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Worksheet — 1.1.1d CPU Performance and Pipelining

8 questions · 20 marks · instantly marked

Q1Explain how an increase in clock speed affects CPU performance and state one disadvantage of increasing clock speed.[3 marks]

✓ Mark scheme

A higher clock speed means more FDE cycles are completed per second [1], so more instructions are executed per second, improving performance [1]. Disadvantage: increased clock speed leads to greater power consumption and heat generation, requiring better cooling [1]. Accept: thermal throttling may reduce effective speed; increased cost.

Q2Explain why adding more processor cores does not always improve performance.[2 marks]

✓ Mark scheme

Additional cores only help if the task has multiple independent threads that can run simultaneously [1]; single-threaded programs cannot benefit from extra cores because they can only use one core at a time [1].

Q3Describe how pipelining improves CPU throughput. Use an example with three instructions to illustrate your answer.[4 marks]

✓ Mark scheme

Pipelining overlaps the fetch, decode and execute stages of multiple instructions [1]; while instruction 1 is being executed, instruction 2 is being decoded and instruction 3 is being fetched simultaneously [1]; without pipelining, each instruction must complete all stages before the next begins (1 instruction every 3 cycles) [1]; with pipelining, the steady-state rate is approximately 1 instruction per clock cycle, greatly increasing throughput [1].

Q4Describe what is meant by a data hazard in a pipeline and explain how operand forwarding can mitigate it.[4 marks]

✓ Mark scheme

A data hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed its execute stage [1]; without mitigation, the pipeline must stall until the result is available [1]; operand forwarding (bypassing) routes the result directly from the output of the ALU to the input of the next instruction before it is written back to a register [1]; this allows the dependent instruction to proceed without waiting for a write-back, eliminating the stall in many cases [1].

Q5Describe what is meant by a control hazard in a pipeline and explain how branch prediction attempts to mitigate it.[4 marks]

✓ Mark scheme

A control hazard occurs when a branch instruction changes the PC, but the pipeline has already fetched/decoded subsequent sequential instructions that may not be needed [1]; this wastes pipeline stages [1]; branch prediction attempts to predict whether the branch will be taken [1]; if the prediction is correct, execution continues without stall; if wrong, the incorrectly loaded instructions are flushed from the pipeline and correct instructions fetched, incurring a penalty [1].

Q6Explain what is meant by a structural hazard and give one technique to prevent it.[2 marks]

✓ Mark scheme

A structural hazard occurs when two pipeline stages require the same hardware resource simultaneously [1], e.g. both the fetch stage and execute stage need to access memory at the same time. Prevention: use separate instruction cache and data cache so fetch and data access do not compete for the same memory resource [1].

Q7A 3-stage pipeline is running a program with many conditional branches. The branch predictor is correct 80% of the time and wrong 20% of the time. Each misprediction causes a 3-cycle penalty. Explain the impact this would have on performance.[2 marks]

✓ Mark scheme

20% of branches are mispredicted, each costing 3 wasted cycles due to the pipeline flush [1]; with a high proportion of branches, the effective throughput will be significantly below the theoretical 1 instruction per cycle, reducing the performance advantage of pipelining [1].

Q8Evaluate the statement: “Doubling the number of CPU cores will always double overall system performance.”[3 marks]

✓ Mark scheme

The statement is not always true [1]; doubling cores can approximately double throughput for tasks that are fully parallelisable (e.g. rendering individual frames or compiling independent files) [1]; however, sequential programs (or programs with little parallelism) cannot utilise more than one core effectively, and Amdahl's Law shows that the speedup is limited by the sequential portion of the code. Additionally, inter-core communication overhead and memory bandwidth limits may reduce the practical gain [1].

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Factors Affecting CPU Performance

Pipelining

Pipeline Hazards

Branch Prediction

Worksheet — 1.1.1d CPU Performance and Pipelining

Mini Test — 1.1.1d CPU Performance and Pipelining