Overview of the Fetch-Decode-Execute Cycle

The CPU continuously repeats the Fetch-Decode-Execute (FDE) cycle to carry out program instructions. Each iteration processes one instruction. The cycle involves several registers working in a precise sequence.

Stage 1: Fetch

The fetch stage retrieves the next instruction from main memory:

1. The contents of the Program Counter (PC) are copied to the Memory Address Register (MAR).
2. The address in the MAR is placed on the address bus; the Control Unit asserts a read signal on the control bus.
3. Main memory responds by placing the instruction at that address onto the data bus.
4. The instruction travels via the data bus to the Memory Data Register (MDR).
5. The contents of the MDR are copied to the Current Instruction Register (CIR).
6. The PC is incremented to point to the next instruction (this can happen concurrently with steps 2–5).

Stage 2: Decode

The Control Unit decodes the instruction held in the CIR:

• The instruction is split into its opcode (operation code — the operation to be performed, e.g. ADD, LOAD, STORE) and operand (the data or address to operate on).
• The CU interprets the opcode and generates the appropriate control signals to activate the correct components.
• If the operand is a memory address, the address is loaded into the MAR so data can be fetched in the execute stage.

Stage 3: Execute

The decoded instruction is carried out:

• If it is an arithmetic or logical instruction: the ALU performs the operation on the operands; the result is stored in the Accumulator (or a general purpose register); the status register flags are updated.
• If it is a memory read: the address is placed on the address bus; data is read from memory into the MDR, then transferred to a register.
• If it is a memory write: the data is transferred from a register to the MDR; the address is placed in the MAR; the data is written to memory via the data bus.
• If it is a branch instruction: the PC is updated with the branch target address (overwriting the normal sequential increment), causing a jump in program execution.

Interrupt Handling (A Level)

At the end of each execute stage, the CU checks the interrupt register (or a dedicated interrupt flag) to see if an interrupt has been raised. Interrupts are signals from hardware or software requesting the CPU's attention (e.g. I/O completed, timer expired, error).

If an interrupt with sufficient priority is pending:

1. The CPU finishes the current instruction.
2. The current values of all registers (PC, CIR, ACC, GPRs, status register) are saved to a special area of memory called the stack — this is called the context save.
3. The PC is loaded with the address of the appropriate Interrupt Service Routine (ISR), obtained from the interrupt vector table.
4. The ISR executes (its own FDE cycle iterations).
5. At the end of the ISR, the saved register values are restored from the stack (context restore), and the PC is restored to where it was before the interrupt, allowing the original program to continue exactly where it left off.